PIC24F16KA101 MICROCHIP [Microchip Technology], PIC24F16KA101 Datasheet
PIC24F16KA101
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PIC24F16KA101 Summary of contents
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... PIC24FXXKAXXX family. Users of any one of these devices should use the development tools that are already supporting the device programming. The programming specifications are specific to the following devices: • PIC24F08KA101 • PIC24F16KA101 • PIC24F08KA102 • PIC24F16KA102 • PIC24F04KA200 • PIC24F04KA201 2.0 PROGRAMMING OVERVIEW ...
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PIC24FXXKAXXX 2.3 Pin Diagrams Figure 2-2 provides the pin diagrams PIC24FXXKAXXX family. FIGURE 2-2: PIN DIAGRAMS 14-Pin SPDIP, SOIC 20-Pin SPDIP, SOIC 28-Pin PDIP, SOIC 28-Pin QFN DS39919A-page 2 Table 2-1 provides the pins that are required for programming (indicated ...
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... TABLE 2-4: PIC24FXXKA1XX Device PIC24F08KA101 map for the PIC24F16KA101 PIC24F08KA102 PIC24F16KA102 Note: An erase operation can be performed on one, four or eight words at a time and a program operation can be performed on one word at a time. Advance Information CONFIGURATION REGISTER ...
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PIC24FXXKAXXX FIGURE 2-3: PROGRAM MEMORY MAP Note 1: The address boundaries for user Flash code memory are device dependent (see Table 2-3). 2: PIC24F04KA2XX devices have no data EEPROM. DS39919A-page 4 000000h User Flash Code Memory (5632 x 24-bit) AFEh/15FEh/2BFEh ...
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DEVICE PROGRAMMING – ICSP The ICSP method is a special programming protocol that allows reading and writing PIC24FXXKAXXX device family memory. ICSP is the most direct method used to program a device; however, Enhanced ICSP is faster. The ICSP ...
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PIC24FXXKAXXX 3.2.1 SIX SERIAL INSTRUCTION EXECUTION The SIX control code allows PIC24FXXKAXXX family assembly instructions. When the SIX code is received, the CPU is suspended for 24 clock cycles as the instruction is then clocked into the internal buffer. Once ...
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FIGURE 3-2: SIX SERIAL EXECUTION PGCx PGDx Execute PC – 1, Fetch SIX Only for Control Code Program Memory Entry ...
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PIC24FXXKAXXX 3.3 Entering ICSP Mode 3.3.1 LOW-VOLTAGE ICSP ENTRY As illustrated in Figure 3-4, the following processes are involved in entering ICSP Program/Verify mode using MCLR: 1. MCLR is briefly driven high, then low 32-bit key sequence is ...
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Flash Memory Programming in ICSP Mode 3.4.1 PROGRAMMING OPERATIONS The NVMCON register controls the Flash memory write and erase operations. To program the device, set the NVMCON register to select the type of erase operation (see Table 3-2) or ...
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PIC24FXXKAXXX TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE Command Data (Binary) (Hex) Step 1: Exit the Reset vector. 0000 000000 NOP 0000 040200 GOTO 0000 000000 NOP Step 2: Set the NVMCON to erase the entire program memory. 0000 ...
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FIGURE 3-7: PACKED INSTRUCTION WORDS IN W0: LSW0 W1 MSB1 W2 LSW1 W3 LSW2 W4 MSB3 W5 LSW3 TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY Command Data (Binary) (Hex) Step 1: Exit the Reset ...
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PIC24FXXKAXXX TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED) Command Data (Binary) (Hex) Step 5: Set the Read Pointer (W6) and load the (next set of) write latches. 0000 EB0300 CLR 0000 000000 NOP 0000 BB0BB6 TBLWTL 0000 ...
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FIGURE 3-8: PROGRAM CODE MEMORY FLOW LoopCount = LoopCount + 1 © 2008 Microchip Technology Inc. PIC24FXXKAXXX Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write ...
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PIC24FXXKAXXX 3.7 Writing Data EEPROM Figure 3-9 illustrates the flow of programming the data EEPROM memory. The procedure is the same as writing code memory. The only difference is that only one word is programmed in each operation. When writing ...
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TABLE 3-6: INSTRUCTION EXECUTION FOR WRITING DATA EEPROM Data Command (Hex) (Binary) Step 1: Exit the Reset vector. 0000 000000 NOP 0000 040200 GOTO 0000 000000 NOP Step 2: Set the NVMCON to program 1 data word. 0000 24004A MOV ...
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PIC24FXXKAXXX 3.8 Writing Configuration Registers The procedure for writing the Configuration registers is the same as for writing code memory. The only differ- ence is that, only one word is programmed in each operation. When writing Configuration registers, one word ...
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TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS Command Data (Binary) (Hex) Step 1: Exit the Reset vector. 0000 000000 NOP 0000 040200 GOTO 0000 000000 NOP Step 2: Initialize the Write Pointer (W7) for the TBLWT instruction. 0000 ...
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PIC24FXXKAXXX 3.9 Reading Code Memory To read the code memory, execute a series of TBLRD instructions and clock out the data using the REGOUT command. Table 3-9 provides the ICSP programming details for reading code memory. In Step 1, the ...
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Reading Data EEPROM Memory The procedure for reading data EEPROM memory is the same as reading the code memory. The only differ- ence is that the 16-bit data words are read instead of the 24-bit words. TABLE 3-10: SERIAL ...
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PIC24FXXKAXXX 3.11 Reading Configuration Memory The procedure for reading a Configuration register is the same as reading the code memory. The only difference is that the 16-bit data words are read (with the upper byte read being all ‘0‘s) instead ...
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Verifying Code Memory, Data EEPROM Memory and Configuration Registers To verify the code memory, read the code memory space and compare it with the copy held in the programmer’s buffer. To verify the data EEPROM and Configuration registers, follow ...
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PIC24FXXKAXXX TABLE 3-12: SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD Command Data (Binary) (Hex) Step 1: Exit Reset vector. 0000 000000 NOP 0000 040200 GOTO 0000 000000 NOP Step 2: Initialize TBLPAG and the Read Pointer (W0) for ...
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DEVICE PROGRAMMING – ENHANCED ICSP This section describes the programming of the device through Enhanced ICSP and the programming executive. The programming executive resides in the executive memory (separate from user memory space), and is executed when Enhanced ICSP ...
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PIC24FXXKAXXX 4.2 Confirming the Presence of the Programming Executive Before beginning programming, confirm programming executive is stored in the executive memory and perform the following: 1. Enter In-Circuit Serial Programming mode (ICSP). 2. Read the unique Application ID Word stored ...
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FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE USING LOW-VOLTAGE ENTRY P6 P14 MCLR V DD PGDx PGCx P18 FIGURE 4-4: ENTERING ENHANCED ICSP™ MODE USING HIGH-VOLTAGE ENTRY PGDx PGCx P18 4.4 Blank Check The term ...
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PIC24FXXKAXXX 4.5.2 PROGRAMMING VERIFICATION After the code memory is programmed, the contents of the memory can be verified to ensure that the programming is successful. Verification requires the code memory to be read back and compared with the copy held ...
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FIGURE 4-6: FLOWCHART FOR PROGRAMMING DATA EEPROM Start RemainingWords = 256 (100h) BaseAddress = 0 Send PROGD Command to Program BaseAddress Is PROGD response PASS? Yes RemainingWords = RemainingWords – 1 BaseAddress = BaseAddress + 02h Are No RemainingWords ‘0’? ...
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PIC24FXXKAXXX 4.7.3 CODE-PROTECT CONFIGURATION BITS The FBS and FGS Configuration registers are special Configuration registers which control the code protection for the boot segment and general segment, respectively. For each segment, two forms of code protection are provided. One form ...
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TABLE 4-2: PIC24FXXKAXXX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register DSWDTPS<3:0> FDS<3:0> DSZPBOR FDS<6> FCKSM<1:0> FOSC<7:6> FNOSC<2:0> FOSCSEL<2:0> Oscillator Selection bits FWDTEN FWDT<7> GSS0 FGS<1> GWRP FGS<0> ICS<1:0> FICD<1:0> Note 1: Applies only to the 28-pin device. 2: The ...
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PIC24FXXKAXXX TABLE 4-2: PIC24FXXKAXXX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register IESO FOSCSEL<7> (1) I2C1SEL FPOR<4> (2) MCLRE FPOR<7> OSCIOFNC FOSC<2> POSCMD<1:0> FOSC<1:0> POSCFREQ<1:0> FOSC<4:3> PWRTEN FPOR<3> RTCCKSEL FDS<5> SOSCSEL FOSC<5> WDTPRE FWDT<4> WDTPOST<3:0> FWDT<3:0> WINDIS FWDT<6> Note 1: ...
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FIGURE 4-7: CONFIGURATION BIT PROGRAMMING FLOW ConfigAddress = ConfigAddress + 2 4.8 Exiting the Enhanced ICSP Mode To exit the Program/Verify mode, remove V MCLR illustrated in Figure 4-8. For exiting interval P16 should elapse between ...
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PIC24FXXKAXXX 5.0 THE PROGRAMMING EXECUTIVE This section describes the programming executive communication, programming executive commands, programming responses, programming programming executive to memory and programming verification. 5.1 Programming Executive Communication The programmer and the programming executive have a master-slave relationship, where ...
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TIME-OUTS The programming executive does not use the Watch- dog Timer or time-out for transmitting responses to the programmer. If the programmer does not follow the flow control mechanism using PGCx, as described in Section 5.1.1 “Communication Interface and ...
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PIC24FXXKAXXX 5.2.2 PACKED DATA FORMAT When 24-bit instruction words are transferred across the 16-bit SPI interface, they are packed to conserve space using the format illustrated in Figure 5-5. This format minimizes the traffic over the SPI and provides the ...
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COMMAND DESCRIPTIONS The commands supported by the programming executive are described in Section 5.2.5 “SCHECK Command” through Section 5.2.13 Command”. 5.2.5 SCHECK COMMAND Opcode Length Field Description Opcode 0h Length 1h The SCHECK command instructs the ...
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PIC24FXXKAXXX 5.2.8 READP COMMAND Opcode Length N Reserved Addr_MSB Addr_LS Field Description Opcode 2h Length 4h N Number of 24-bit instructions to read (max. of 32768). Reserved 0h Addr_MSB MSb of 24-bit source address. Addr_LS ...
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Expected Response (2 words): 1F00h 0002h Note: Refer to Table 2-4 for data EEPROM memory size information. 5.2.11 PROGP COMMAND Opcode Length Reserved Addr_MSB Addr_LS D_1 D_2 ... D_48 Field Description Opcode 5h Length 33h ...
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PIC24FXXKAXXX 5.2.13 QVER COMMAND Opcode Length Field Description Opcode Bh Length 1h The QVER command queries the version of the programming executive software stored in the test memory. The “version.revision” information is returned in the response‘s QE_Code ...
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QE_Code Field The QE_Code is a byte in the first word of the response. This byte is used to return data for query commands and error codes for all of the other commands. When the programming executive processes one ...
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PIC24FXXKAXXX TABLE 5-5: PROGRAMMING THE PROGRAMMING EXECUTIVE Command Data (Binary) (Hex) Step 1: Exit Reset vector and erase the executive memory. 0000 000000 NOP 0000 040200 GOTO 0000 000000 NOP Step 2: Initialize pointers to read Diagnostic Words for storage ...
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TABLE 5-5: PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED) Command Data (Binary) (Hex) Step 10: Load W0:W2 with the next two words of packed programming executive code. 0000 2<LSW0>0 MOV 0000 2<MSB1:MSB0>1 MOV 0000 2<LSW1>2 MOV Step 11: Set the Read Pointer ...
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PIC24FXXKAXXX TABLE 5-5: PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED) Command Data (Binary) (Hex) Step 18: Load the saved Diagnostic Words in last eight write latches. 0000 BB1A86 TBLWTL 0000 000000 NOP 0000 000000 NOP 0000 BB1A87 TBLWTL 0000 000000 NOP 0000 ...
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TABLE 5-6: READING EXECUTIVE MEMORY Command Data (Binary) (Hex) Step 1: Exit the Reset vector. 0000 000000 NOP 0000 040200 GOTO 0000 000000 NOP Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction. 0000 200800 MOV 0000 ...
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... Table 6-1 provides the Device ID for each device; Table 6-2 provides the Device ID registers; Table 6-3 describes the bit field of each register. TABLE 6-1: DEVICE IDs Device ID DEVID PIC24F08KA101 0D08h PIC24F16KA101 0D01h PIC24F08KA102 0D0Ah PIC24F16KA102 0D03h PIC24F04KA200 0D02h PIC24F04KA201 0D00h ...
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AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS TABLE 7-1: STANDARD OPERATING CONDITIONS Standard Operating Conditions Operating Temperature: 0°C to +70°C and programming: +25°C is recommended. Param Symbol Characteristic No. D111 V Supply Voltage During Programming DD D112 I Programming Current on ...
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PIC24FXXKAXXX TABLE 7-1: STANDARD OPERATING CONDITIONS (CONTINUED) Standard Operating Conditions Operating Temperature: 0°C to +70°C and programming: +25°C is recommended. Param Symbol Characteristic No. Delay Between PGDx ↓ by Programming P20 T 11 DLY Executive and First PGCx↑ of Reception ...
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families ...
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W ORLDWIDE AMERICAS ASIA/PACIFIC Corporate Office Asia Pacific Office 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Chandler, AZ 85224-6199 Tower 6, The Gateway Tel: 480-792-7200 Harbour City, Kowloon Fax: 480-792-7277 Hong Kong Technical Support: Tel: 852-2401-1200 http://support.microchip.com Fax: 852-2401-3431 ...