ATMEGA169 ATMEL [ATMEL Corporation], ATMEGA169 Datasheet - Page 184

• Manufacturer Part Number: ATMEGA169
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

184
ATmega169/V
Figure 80. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram (Figure 80.), a bus transfer involves the following steps:
1. The a start condition is generated by the Master by forcing the SDA low line while
2. In addition, the start detector will hold the SCL line low after the Master has
3. The Master set the first bit to be transferred and releases the SCL line (C). The
4. After eight bits are transferred containing slave address and data direction (read
5. If the Slave is addressed it holds the SDA line low during the acknowledgment
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition
If the Slave is not able to receive more data it does not acknowledge the data byte it has
last received. When the Master does a read operation it must terminate the operation by
force the acknowledge bit low after the last byte transmitted.
Figure 81. Start Condition Detector, Logic Diagram
SDA
SCL
the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of
the Shift Register, or by setting the corresponding bit in the PORT Register to
zero. Note that the Data Direction Register bit must be set to one for the output to
be enabled. The slave device’s start detector logic (Figure 81.) detects the start
condition and sets the USISIF Flag. The flag can generate an interrupt if
necessary.
forced an negative edge on this line (B). This allows the Slave to wake up from
sleep or complete its other tasks before setting up the Shift Register to receive
the address. This is done by clearing the start condition flag and reset the
counter.
Slave samples the data and shift it into the Serial Register at the positive edge of
the SCL clock.
or write), the Slave counter overflows and the SCL line is forced low (D). If the
slave is not the one the Master has addressed, it releases the SCL line and waits
for a new start condition.
cycle before holding the SCL line low again (i.e., the Counter Register must be
set to 14 before releasing SCL at (D)). Depending of the R/W bit the Master or
Slave enables its output. If the bit is set, a master read operation is in progress
(i.e., the slave drives the SDA line) The slave can hold the SCL line low after the
acknowledge (E).
is given by the Master (F). Or a new start condition is given.
Write( USISIF)
S
A B
C
ADDRESS
SDA
SCL
1 - 7
R/W
8
D
ACK
9
E
DATA
1 - 8
D Q
CLR
ACK
9
D Q
CLR
DATA
1 - 8
USISIF
CLOCK
HOLD
ACK
9
2514P–AVR–07/06
F
P