P80C32EBBB PHILIPS [NXP Semiconductors], P80C32EBBB Datasheet - Page 46

• Manufacturer Part Number: P80C32EBBB
• Description: CMOS single-chip 8-bit microcontrollers
• Manufacturer: PHILIPS [NXP Semiconductors]

1. L = Level activated
2. T = Transition activated
Philips Semiconductors
Interrupt Priority Structure
The 80C52/54/58 has a 6-source four-level interrupt structure. There
are 3 SFRs associated with the interrupts on the 80C52/54/58. They
are the IE and IP. (See Figures 10 and 11.) In addition, there is the
IPH (Interrupt Priority High) register that makes the four-level
interrupt structure possible. The IPH is located at SFR address B7H.
The structure of the IPH register and a description of its bits is
shown below:
IPH (Interrupt Priority High) (B7H)
IPH.0 PX0H External interrupt 0 priority high
IPH.1 PT0H Timer 0 interrupt priority high
IPH.2 PX1H External interrupt 1 priority high
IPH.3 PT1H Timer 1 interrupt priority high
IPH.4 PSH
IPH.5 PT2H Timer 2 interrupt priority high
IPH.6 —
IPH.7 —
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
Table 7.
NOTES:
1996 Aug 16
CMOS single-chip 8-bit microcontrollers
7
–
SOURCE
PCA
6
–
SP
X0
T0
X1
T1
T2
Serial Port interrupt high
Not implemented
Not implemented
Interrupt Table
PT2H
5
PSH
Figure 9. UART Multiprocessor Communication, Automatic Address Recognition
4
POLLING PRIORITY
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
D0
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
RECEIVED ADDRESS D0 TO D7
PT1H
3
PROGRAMMED ADDRESS
1
2
3
4
5
6
7
D1
PX1H
2
D2
PT0H
1
SM0
1
1
D3
PX0H
REQUEST BITS
0
SM1
TF2, EXF2
CF, CCFn
1
0
n = 0–4
R1, TI
D4
TP0
TF1
IE0
IE1
16
SM2
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels on the
80C52/54/58 rather than two as on the 80C51. An interrupt will be
serviced as long as an interrupt of equal or higher priority is not
already being serviced. If an interrupt of equal or higher level priority
is being serviced, the new interrupt will wait until it is finished before
being serviced. If a lower priority level interrupt is being serviced, it
will be stopped and the new interrupt serviced. When the new
interrupt is finished, the lower priority level interrupt that was
stopped will be completed.
COMPARATOR
D5
1
IPH.x
PRIORITY BITS
0
0
1
1
REN
1
D6
HARDWARE CLEAR?
N (L)
TB8
N (L) Y (T)
D7
IP.x
X
0
1
0
1
1
Y
Y
N
N
N
Y (T)
RB8
80C52/80C54/80C58
D8
Level 0 (lowest priority)
Level 1
Level 2
Level 3 (highest priority)
2
INTERRUPT PRIORITY LEVEL
INTERRUPT PRIORITY LEVEL
TI
VECTOR ADDRESS
RI
Product specification
0BH
1BH
2BH
03H
13H
23H
33H
SCON
(98H)
SU00045