LPC1754 NXP [NXP Semiconductors], LPC1754 Datasheet - Page 53

no-image

LPC1754

Manufacturer Part Number
LPC1754
Description
32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
Manufacturer
NXP [NXP Semiconductors]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC1754FBD
Manufacturer:
NXP
Quantity:
5 000
Part Number:
LPC1754FBD80
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
LPC1754FBD80
0
Company:
Part Number:
LPC1754FBD80
Quantity:
6 000
Company:
Part Number:
LPC1754FBD80
Quantity:
10
Company:
Part Number:
LPC1754FBD80
Quantity:
5 000
Part Number:
LPC1754FBD80,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC1754FBD80,518
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
LPC1754FBD80,551
Quantity:
9 999
Part Number:
LPC1754FBD80,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC1754FBD80,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
LPC1754FBD80K
0
NXP Semiconductors
12. ADC electrical characteristics
Table 16.
V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
LPC1759_58_56_54_52_51_4
Product data sheet
Symbol
V
C
E
E
E
E
E
R
f
f
clk(ADC)
c(ADC)
DDA
IA
D
L(adj)
O
G
T
ia
vsi
Conditions: V
The ADC is monotonic, there are no missing codes.
The differential linearity error (E
The integral non-linearity (E
appropriate adjustment of gain and offset errors. See
The offset error (E
ideal curve. See
The gain error (E
error, and the straight line which fits the ideal transfer curve. See
The absolute error (E
ADC and the ideal transfer curve. See
See
= 2.7 V to 3.6 V; T
Figure
ADC characteristics
Parameter
analog input voltage
analog input capacitance
differential linearity error
integral non-linearity
offset error
gain error
absolute error
voltage source interface
resistance
ADC clock frequency
ADC conversion frequency
22.
SSA
Figure
G
= 0 V, V
O
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
T
amb
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
21.
Fig 20. SPI slave timing (CPHA = 0)
DDA
=
L(adj)
= 3.3 V.
40
D
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
) is the difference between the actual step width and the ideal step width. See
°
C to +85
Figure
SCK (CPOL = 0)
SCK (CPOL = 1)
Conditions
°
21.
C unless otherwise specified; ADC frequency 13 MHz.
MOSI
MISO
Rev. 04 — 26 January 2010
Figure
21.
Figure
DATA VALID
DATA VALID
t
SPIQV
LPC1759/58/56/54/52/51
21.
[1][2][3]
[1][4]
[1][5]
[1][6]
[1][7]
[8]
T
SPICYC
Min
0
-
-
-
-
-
-
-
-
-
t
32-bit ARM Cortex-M3 microcontroller
SPIDSU
DATA VALID
DATA VALID
t
SPICLKH
t
Typ
-
-
-
-
±2
-
-
-
-
-
SPIDH
t
SPICLKL
t
002aad989
SPIOH
Max
V
15
±1
±3
-
0.5
4
7.5
13
200
Figure
© NXP B.V. 2010. All rights reserved.
DDA
21.
Unit
V
pF
LSB
LSB
LSB
%
LSB
MHz
kHz
53 of 64

Related parts for LPC1754