W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 145

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

Interrupt Identification Register (IIR)
FMES [7]: FIFO Mode Enable Status
This bit indicates whether the FIFO mode is enabled or not. Since the FIFO mode is always enable,
this bit always shows the logical 1 when CPU is reading this register.
RFTLS [6:5]: RX FIFO Threshold Level Status
These bits show the current setting of receiver FIFO threshold level (RTHO). The meaning of RTHO is
defined in the following FCR description.
DMS [4]: DMA Mode Select
The DMA function is not implemented in this version. When reading IIR, the DMS is always returned
0.
IID [3:1]: Interrupt Identification
The IID together with NIP indicates the current interrupt request from UART.
NIP [0]: No Interrupt Pending
There is no pending interrupt.
Table 6.9.1 Interrupt Control Functions
Note: These definitions of bit 7, bit 6, bit 5, bit 4 are different from the 16550.
REGISTER
IIR [3:0]
- - - 1
0110
0100
1100
0010
0000
FMES
IIR
7
PRIORITY
0xFFF8.0008
Highest
Second
Second
Fourth
Third
ADDRESS
--
6
RFTLS
Receiver FIFO Time-
INTERRUPT TYPE
Receiver Line Status
Available (Irpt_RDA)
Transmitter Holing
out (Irpt_TOUT)
Register Empty
MODEM Status
Received Data
(Irpt_THRE)
(Irpt_MOS)
(Irpt_RLS)
R/W
5
None
R
Interrupt Identification Register
DMS
4
Overrun error, parity error, framing
error, or break interrupt
Receiver FIFO threshold level is
reached
Receiver FIFO is non-empty and
no activities are occurred in the
receiver FIFO during the TOR
defined time duration
Transmitter holding register empty
The CTS, DSR, or DCD bits are
changing state or the RI bit is
changing from high to low.
- 142 -
INTERRUPT SOURCE
W90N740CD/W90N740CDG
DESCRIPTION
3
None
IID
2
Reading the LSR
Receiver FIFO drops below
the threshold level
Reading the RBR
Reading the IIR (if source of
interrupt
writing into the THR
Reading the MSR
INTERRUPT RESET
1
CONTROL
is
RESET VALUE
0x8181.8181
--
Irpt_THRE)
NIP
0
or