X40434 INTERSIL [Intersil Corporation], X40434 Datasheet
X40434
Related parts for X40434
X40434 Summary of contents
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... X40430, X40431, X40434, X40435 May 24, 2006 DESCRIPTION The X40430, X40431, X40434, X40435 combines power-on reset control, watchdog timer, supply voltage supervision, second and third voltage supervision, manual reset, and Block Lock in one package. This combination lowers system cost, reduces board space requirements, and increases reliability ...
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... Device Voltages X40430, X40431 -A 5V 3.3V; 1.8V -B 5V; 3V; 1.8V -C 3.3V; 2.5V; 1.8V X40434, X40435 -A 5V; 3.3V; 1. 3.3V; 1. 3.3V; 1.2V *Voltage monitor requires Vcc to operate. Others are independent of Vcc. 2 X40430, X40431, X40434, X40435 + V V3 Monitor TRIP3 - Logic V CC V2MON Monitor V TRIP2 Logic - Fault Detection Register Status ...
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... X40434V IB 1.3 to 5.5 X40434V14IZ-B X4043 4V ZIB 1.3 to 5.5 (Note) X40434S14-A X40434S A 1.3 to 5.5 X40434S14Z-A X40434S ZA 1.3 to 5.5 (Note) X40434S14I-A X40434S IA 1.3 to 5.5 X40434S14IZ-A X40434S ZIA 1.3 to 5.5 (Note) 3 X40430, X40431, X40434, X40435 V V TRIP1 TRIP2 RANGE RANGE RANGE 2.9V ±50mV 2.2V ±50mV 1.7V ±50mV 4.4V ±50mV 2.6V ±50mV 4.6V ±50mV 1.0V ±50mV 2.9V ±50mV 1.3V ±50mV 3.1V ±50mV V TEMP. TRIP3 RANGE RANGE (° ...
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... X40431V B X40431V14Z-B X40431V ZB (Note) X40431V14I-B X40431V IB X40431V14IZ-B X40431V ZIB (Note) X40435S14-C X40435 C 1.0 to 5.5 X40435S14I-C X40435 IC X40435V14-C X40435 C X40435V14I-C X40435 IC 4 X40430, X40431, X40434, X40435 V V TRIP1 TRIP2 RANGE RANGE RANGE 4.6V ±50mV 1.3V ±50mV 3.1V ±50mV 2.9V ±50mV 1.7V ±50mV 2.9V ±50mV 2.2V ±50mV 1.7V ±50mV 4.4V ±50mV 2.6V ±50mV 4.6V ±50mV 1.0V ± ...
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... NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5 X40430, X40431, X40434, X40435 V V TRIP1 ...
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... RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW when- ever V falls below V RESET CC grammed time period (t t thereafter. PURST RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when- ever V falls below V CC grammed time period (t t thereafter. PURST 7 ...
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... It also remains active until V2MON returns and exceeds V cuitry monitors the power supply connected to V2MON pin For the X40434 and X40435, the V2FAIL signal remains active until V active until V2MON returns and exceeds V sense circuitry is powered by V cannot be monitored. ...
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... Start, Clock Low, Clock High and Stop. The state of two nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor can change these watch- dog bits by writing to the X40430, X40431, X40434, X40435 control register (also refer to page 20). 8 X40430, X40431, X40434, X40435 ...
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... The user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores WD1, WD0, PUP1, PUP0, and BP. The X40430, X40431, X40434, X40435 will not acknowledge any data bytes written after the first byte is entered. TRIPX The state of the Control Register can be read at any ...
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... The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a vola- tile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, 10 X40430, X40431, X40434, X40435 1 14 RESET 6 ...
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... X40430, X40431, X40434, X40435 – Write one byte value to the Control Register that has all the control bits set to the desired state. The Control register can be represented as qxys 001r in binary, where xy are the WD bits the BP bit and qr are the power-up bits ...
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... V . TRIP3 Figure 8. Valid Start and Stop Conditions SCL SDA 12 X40430, X40431, X40434, X40435 Data Stable Data Change SERIAL INTERFACE Interface Conventions The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver ...
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... Signals from the Master SDA Bus Signals from the Slave 13 X40430, X40431, X40434, X40435 detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state. Serial Write Operations Byte Write For a write operation, the device requires the Slave Address Byte and a Word Address Byte ...
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... Figure 12. Writing 12 bytes to a 16-byte page starting at location 10. 7 Bytes address = 6 14 X40430, X40431, X40434, X40435 Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal stop is ...
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... SDA HIGH during the ninth clock cycle and then issue a stop condition. 15 X40430, X40431, X40434, X40435 Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “ ...
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... Where for Array for Control Register or Fault Detection Register. – next two bits are ‘0’. – next bit that becomes the MSB of the address. Figure 14. X40430, X40431, X40434, X40435 Addressing Slave Byte General Purpose Memory 1 ...
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... Master r t SDA Bus Signals from the Slave Figure 17. Sequential Read Sequence Slave Signals from Address the Master SDA Bus Signals from K the Slave 17 X40430, X40431, X40434, X40435 S Slave Byte t a Address Address ...
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... V3FAIL, WDO) V Output (RESET, LOWLINE) HIGH OH Voltage 18 X40430, X40431, X40434, X40435 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied ...
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... Based on characterization data. EQUIVALENT INPUT CIRCUIT FOR VxMON ( ∆V VxMON V ref CAPACITANCE Symbol (1) C Output Capacitance (SDA, RESET/RESET, LOWLINE, OUT V2FAIL,V3FAIL, WDO) (1) C Input Capacitance (SCL, WP, MR) IN Note: (1) This parameter is not 100% tested. 19 X40430, X40431, X40434, X40435 (Continued) (4) Min Typ 2.0 4.55 4.6 4.35 4.4 2.85 2.9 1.7 0.9 2.85 2.9 2.55 2.6 2.15 2.2 1 ...
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... SDA and SCL Fall Time Setup Time SU: Hold Time HD:WP Cb Capacitive load for each bus line Note: ( total capacitance of one bus line in pF. 20 X40430, X40431, X40434, X40435 SYMBOL TABLE WAVEFORM V2MON, V3MON 4.6kΩ V2FAIL, V3FAIL 30pF ...
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... the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 21 X40430, X40431, X40434, X40435 t t HIGH ...
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... V V2MON V3MON F CC V2MON V3MON R CC Reset Valid V RVALID CC ( RESET/ RESET delay (activation only X40430, X40431, X40434, X40435 t RPDL t RPDX t RPDL t RPDX V RVALID t RPD1 IN1 Parameters to V3FAIL ( TRIP3 Fall Time Rise Time t RPDL t RPDX ...
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... Notes: ( 25°C. CC (2) Values based on characterization data only. Watchdog Time Out For 2-Wire Interface Start SCL SDA WDO Minimum Sequence to Reset WDT SCL SDA 23 X40430, X40431, X40434, X40435 Parameters Start Clockin ( RSP < t WDO Start = 5V) (CONTINUED) CC (1) ...
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... Programming Voltage Set Voltage Range TRAN1 TRIP1 V V Set Voltage Range – X40430, X40431 TRAN2 TRIP2 V V Set to Voltage Range – X40434, X40435 TRAN2A TRIP2 V V Set Voltage Range TRAN3 TRIP3 V V Set Voltage variation after programming (-40 to +85°C). tv TRIPX t ...
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... Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 25 X40430, X40431, X40434, X40435 D (N/2)+1 (N/2) H ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 26 X40430, X40431, X40434, X40435 M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC M ...