ATA5749_09 ATMEL [ATMEL Corporation], ATA5749_09 Datasheet - Page 6

• Manufacturer Part Number: ATA5749_09
• Description: Fractional-N PLL Transmitter IC
• Manufacturer: ATMEL [ATMEL Corporation]

3.3
3.4
6
Crystal Oscillator
Clock Driver
ATA5749 [Preliminary]
The crystal oscillator (XTO) is an amplitude-regulated Pierce oscillator. It has fixed function and
is not programmable. The oscillator is enabled when the EN is “set”. After the oscillator’s output
amplitude reaches an acceptable level, the XTO_RDY flag is “set”. The CLK-pin becomes active
if CLK_ON is set. The PLL receives its reference frequency.
Typically, this process takes about 200 µs when using a small sized crystal with a motional
capacitance of 4 fF. This start-up time strongly depends on the motional capacitance of the crys-
tal and is lower with higher motional capacitance.
The high negative starting impedance of R
ure rate due to the “sleeping crystal” phenomena (more common among very small sized
3.2 mm
The clock driver block shown in
CLK_ON, and DIV_CNTRL bits in the configuration register. When CLK_ONLY is “clear”, normal
operation is selected and the fractional-N PLL is operating. When CLK_ON is “set”, the CLK out-
put is enabled. The crystal clock divider ratio can be set to divide by 4 when DIV_CNTRL is “set”
and divide by 8 when DIV_CNTRL is “clear”. With a 13.0000 MHz crystal, this yields an output of
3.25 MHz or 1.625 MHz, respectively. When CLK_ON is “clear”, no clock is available at CLK and
the transmitter has less current consumption.
The CLK signal can be used to clock a microcontroller. It is CMOS compatible and can drive up
to 20 pF of load capacitance at 1.625 MHz and up to 10 pF at 3.25 MHz. When the device is in
power-down mode, the CLK output stays low. Upon power up, CLK output remains low until the
amplitude detector of the crystal oscillator detects sufficient amplitude and XTO_RDY and
CLK_ON are “set”. After this takes place, CLK output becomes active. The CLK output is syn-
chronized with the XTO_RDY signal so that the first period of the CLK output is always a full
period (no CLK output spike at activation).
To lower overall current consumption, it is possible to power down the entire chip except for the
crystal oscillator block. This can be achieved when the CLK_ONLY is “set”.
2.5 mm crystals).
Figure 1-1 on page 2
XTO12_START
> 1500 is important to minimize the fail-
is programmed using the CLK_ONLY,
9128D–RKE–01/09