AK5380VT AKM [Asahi Kasei Microsystems], AK5380VT Datasheet - Page 11

• Manufacturer Part Number: AK5380VT
• Description: 96kHz 24Bit ADC with Single - ended Input
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
n System Clock Input
The external clocks which are required to operate the AK5380 are MCLK(256fs/384fs/512fs/768fs), LRCK(1fs), SCLK.
MCLK should be synchronized with LRCK but the phase is not critical. When 384fs, 512fs or 768fs clock is input to
MCLK pin, the internal master clock becomes 256fs(=384fs x 2/3=512fs x 1/2=768fs x 1/3). Table 1 illustrates standard
audio word rates and corresponding frequencies used in the AK5380.
All external clocks (MCLK,BICK,LRCK) should always be present whenever the AK5380 is in normal operation mode
(PDN = “H”). If these clocks are not provided, the AK5380 may draw excess current and may not possibly operate
properly because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK5380
should be in the power-down mode (PDN = “L”). After exiting reset at power-up etc., the AK5380 is in the power-down
mode until MCLK and LRCK are input.
n Serial Data Interface
Two kinds of data format can be selected by DIF pin. The data is clocked out via the SDTO pin by SCLK corresponding
to the setting of DIF pin. The format of output data is 2’s complement MSB first.
MS0100-E-01
32.0kHz
44.1kHz
48.0kHz
96.0kHz
Mode
fs
0
1
11.2896MHz
12.2880MHz
24.5760MHz
8.1920MHz
DIF
256fs
0
1
24bit, I2S,
24bit, MSB justified, L/R, SCLK 48fs (16bit, MSB justified, L/R, SCLK=32fs)
12.2880MHz
16.9344MHz
18.4320MHz
36.8640MHz
384fs
Table 2. Audio Serial Interface Formats
Table 1. Example of System Clock
OPERATION OVERVIEW
MCLK
16.3840MHz
22.5792MHz
24.5760MHz
512fs
N/A
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SCLK 48fs (16bit, I2S,
33.8688MHz
36.8640MHz
Format
24.576MHz
768fs
N/A
2.0480MHz
2.8224MHz
3.0720MHz
6.1440MHz
64fs
SCLK
SCLK=32fs)
4.0960MHz
5.6448MHz
6.1440MHz
128fs
N/A
[AK5380]
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