78P2342-IGT TERIDIAN [Teridian Semiconductor Corporation], 78P2342-IGT Datasheet - Page 8

• Manufacturer Part Number: 78P2342-IGT
• Description: 2-port E3/DS3/STS-1 LIU with Jitter Attenuator
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

78P2342JAT
2-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION
LEGEND
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
Page 8 of 36
BIT
TYPE
7
6
5
4
3
2
1
0
R/O
ENDECB
REGEN
RCLKP
TCLKP
NAME
RSVD
SRST
DS3
DESCRIPTION
Read only
E3
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/O
VALUE
DFLT
X
X
--
0
0
0
0
0
(continued)

2005 Teridian Semiconductor Corporation
Register Control Enable:
NOTE: Pin 15 (ENDECB) must be tied low when REGEN is enabled.
Line Speed Selection:
Selects the line speed of all channels as well as the input clock frequency
at the CKREF pin.
[DS3 E3] = 00 : STS-1 (51.840MHz)
NOTE: The default values of these register bits depend on the state of
the MSL0 pin upon power-up or reset.
Encoder/Decoder Disable:
NOTE: Relevant only when the REGEN bit is set. Otherwise, ENDECB
pin selection prevails.
RCLK Polarity Selection:
TCLK Polarity Selection:
Reserved
Register Soft-Reset:
When this bit is set, all registers are reset to their default values. Also
resets Jitter Attenuator to “centered” states.
clearing.
0 : Pin selection overrides register settings
1 : Device is controlled via register set.
0 : selects NRZ digital data interface
1 : selects AMI digital data interface
0 : Receive Data clocked out on the falling-edge of RCLK
1 : Receive Data clocked out on the rising-edge of RCLK
0 : Transmit Data clocked in on the rising-edge of TCLK
1 : Transmit Data clocked in on the falling-edge of TCLK
01 : E3 (34.368MHz)
10 : DS3 (44.736MHz)
11 : STS-1 (51.840MHz)
TYPE
R/W
DESCRIPTION
Read or Write
DESCRIPTION
This register bit is self-
Rev 2.2