78P2351-IGT TERIDIAN [Teridian Semiconductor Corporation], 78P2351-IGT Datasheet - Page 17

• Manufacturer Part Number: 78P2351-IGT
• Description: Single Channel OC-3/ STM1-E/ E4 LIU
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

LEGEND
TYPE
TRANSMITTER PINS
NAME
PI0D
PI1D
PI2D
PI3D
PICK
PTOCK
SIDP
SIDN
SICKP
SICKN
CMIP
CMIN
CMI2P
CMI2N
TXCKP
TXCKN
ECLP
ECLN
Page: 17 of 42
CIU
CID
CIS
CIT
PIN DESCRIPTION
CI
PI
A
DESCRIPTION
Analog Pin
(Tie unused pins to ground)
CMOS Schmitt Trigger Input
(Tie unused pins to ground)
CMOS Digital Input
(Tie unused pins to ground)
CMOS Digital Input w/ Pull-up
CMOS Digital Input w/ Pull-down
3-State CMOS Digital Input
LVPECL-Compatible Differential Input
(Tie unused pins to ground)
PIN
100
24
25
26
27
23
28
93
94
79
78
96
97
99
8
9
5
6
TYPE
CIS
CO
PO
PO
CI
PI
PI
A
A
DESCRIPTION
Transmit (Parallel Mode) Data Input:
Four-bit CMOS parallel (nibble) inputs. Data is latched in on the rising edge
(default) of the transmit parallel clock and serialized with the MSB (PIx3D)
transmitted first.
Transmit (Parallel Mode) Clock Input:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock input that must be
source synchronous with the reference clock supplied at the CKREFP/N pins.
Used only in Slave Parallel Mode and Loop-timing Parallel Mode.
Transmit (Parallel Mode) Clock Output:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output that is
intended to latch in synchronous parallel data. Active during reset. Used only
in Master Parallel Mode (output disabled in all other transmit modes).
Transmit (Serial Mode) Data Input:
Differential NRZ data input. See Transmitter Operation section for more info
on different clocking/timing modes.
Transmit (Serial Mode) Clock Input:
A 155.52MHz synchronous differential input clock used to clock in the serial
NRZ data. By default, data is clocked in on the rising edge of SICKP.
Transmit (CMI Mode) Analog Data Output:
A CMI encoded data signal output conforming to the relevant ITU-T G.703
pulse templates when properly terminated and transformer coupled to 75Ω
cable.
undefined during reset.
Transmit Monitor Output:
Redundant CMI transmit driver enabled by RCSL control.
Transmit (Serial Mode) Clock Output:
A 2x line rate LVPECL clock output used to clock out the transmit CMI data.
Used for diagnostics or far end re-timing. Active during reset.
Transmit (Optical Mode) LVPECL Data Output:
Transmit data outputs used for interfacing with optical transceiver modules
when in Fiber (NRZ pass through) mode.

2006 Teridian Semiconductor Corporation
Outputs are tri-stated when transmitter is disabled. Active, but
TYPE
COZ
CO
OD
PO
G
S
DESCRIPTION
LVPECL-Compatible Differential Output
(Tie unused pins to supply or leave floating)
CMOS Digital Output
(Leave unused pins floating)
CMOS Tristate Digital Output
(Leave unused pins floating)
Open-drain Digital Output
(Leave unused pins floating)
Supply
Ground
OC-3/ STM1-E/ E4 LIU
Single Channel
78P2351
Rev. 2.4