ISPPAC30-01SI LATTICE [Lattice Semiconductor], ISPPAC30-01SI Datasheet - Page 27

• Manufacturer Part Number: ISPPAC30-01SI
• Description: In-System Programmable Analog Circuit
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the
function of three required and six optional instructions. Any additional instructions are left exclusively for the manu-
facturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only
the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec-
tively). The ispPAC30 contains the required minimum instruction set as well as one from the optional instruction set.
In addition, there are several proprietary instructions that allow the device to be configured and verified. For
ispPAC30, the instruction word length is six bits. All ispPAC30 instructions available to users are shown in Table 6.
Table 6. ispPAC30 TAP Instructions Table
BYPASS is one of the three required JTAG instructions. It selects the Bypass Register to be connected between
TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the
ispPAC30. The bit code of this instruction is defined to be all ones by the IEEE 1149.1 standard. With ispPAC30,
any instruction beginning with a one will default to BYPASS.
The JTAG required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between
TDI and TDO. The ispPAC30 has no boundary-scan register, so for compatibility it defaults to the BYPASS mode
whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 6.
The EXTEST (external test) instruction is JTAG required and would normally place the device into an external
boundary test mode while also enabling the Boundary-Scan Register to be connected between TDI and TDO.
Again, since the ispPAC30 has no boundary-scan logic, the device is put in the BYPASS mode to ensure specifica-
tion compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros.
The optional IDCODE (identification code) instruction is incorporated in the ispPAC30 and leaves it in its functional
mode when executed. It selects the Device Identification Register to be connected between TDI and TDO. The
Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, device type
and version code (see Figure 12). Access to the Identification Register is immediately available, via a TAP data
RELOADCFG
ERASECFG
ERASEUES
LATCHCFG
Instruction
POWERDN
ADDCFGQ
PROGUES
PROGCFG
POWERUP
READCFG
PROGESF
READUES
ADDCFG
ADDUES
SAMPLE
EXTEST
IDCODE
BYPASS
ENCAL
CFGBE
000000
000001
000010
000011
000101
000110
001010
001011
001100
001101
010001
010010
010011
010110
010111
011011
011100
011101
011110
111111
Code
External Test. Defaults to BYPASS.
Address CFG data register (112 bits).
Address CFG Quick data register (40 bits).
Address UES data register (16 bits).
Latch CFG register into control SRAM.
Read CFG from E
Read UES from E
Program shift register contents into UES E
Program shift register contents into CFG E
Address Identification Code data register.
Program the Electronic Security Fuse bit.
Command a Power Down sequence.
Command a Power Up sequence.
Load CFG E
Erase the CFG/CFGQ E
Erase the UES E
Enable a Calibration sequence.
Bulk erase all E
Sample/Preload. Default to BYPASS.
Bypass (connect TDI to TDO).
27
2
into control SRAM.
2
2
memory (CFG, UES and ESF).
2
2
memory.
Description
prior to ADDUES command.
prior to ADDCFG command.
2
memory.
ispPAC30 Preliminary Data Sheet
2
2
.
.