ISPPACCLK5510V-01T100C LATTICE [Lattice Semiconductor], ISPPACCLK5510V-01T100C Datasheet - Page 18

• Manufacturer Part Number: ISPPACCLK5510V-01T100C
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
  
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
where
Note that because the feedback may be taken from any V divider, V
Because the VCO has an operating frequency range spanning 320 MHz to 640 MHz, and the V dividers provide
division ratios from 2 to 64, the ispClock5500 can generate output signals ranging from 5MHz to 320 MHz. For per-
formance and stability reasons, however, there are several constraints which should be followed when selecting
divider values:
Output Duty Cycle
The ispClock5500’s output duty cycle varies as a function of the V divider used to generate that output. If the V-
divider setting is either 2 or a multiple of 4, the nominal output duty cycle will be exactly 50%. All other V divider set-
tings will result in non-50% output duty cycles. Table 3 summarizes the nominal output duty cycle as a function of
the V divider setting. Note that if the output is inverted, the duty cycle will be equal to 100%-DC%, where DC% is
the duty cycle indicated in the table. For example, with a V divider of 14, the non-inverted duty cycle from Table 3
will be 43%. For an inverted output, the duty cycle will be 100%-43% or 57%.
Table 3. Nominal Output Duty Cycle vs. V-Divider Setting
f
f
M and N are the input and feedback divider settings
V
V
• Use the smallest feasible value for the M divider
• The output frequency from the M (and N) divider should be greater or equal to 10 MHz.
• The product of the N divider and the V divider used to close the PLL’s feedback loop should be less than or
k
ref
fbk
k
equal to 64 (N x V
is the frequency of V divider k
is the setting of the V divider used to provide output k
is the input reference frequency
is the setting of the V divider used to close the PLL feedback path
fbk
≤ 64)
with 50% Output
Divider Settings
12
16
20
24
28
32
36
40
44
48
52
56
60
64
V
2
4
8
Duty Cycle
DC%
50
18
Non-50% Output Duty
Divider Settings with
10
14
18
22
26
30
34
38
42
46
50
54
58
62
V
6
k
and V
Cycles
ispClock5500 Family Data Sheet
fbk
DC%
33
40
43
44
45
46
47
47
47
48
48
48
48
48
48
may refer to the same divider.