HV57708_07 SUTEX [Supertex, Inc], HV57708_07 Datasheet

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HV57708_07

Manufacturer Part Number
HV57708_07
Description
32MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs
Manufacturer
SUTEX [Supertex, Inc]
Datasheet
1.HV57708_07.pdf (7 pages)
Features
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General Description
The HV57708 is a low voltage serial to high voltage
parallel converter with push-pull outputs. The device has
been designed for use as a driver for EL displays. It can
also be used in any application requiring multiple output
high voltage current sourcing and sinking capability such
as driving plasma panels, vacuum fl uorescent displays, or
large matrix LCD displays.
Functional Block Diagram
HVCMOS
5.0V CMS Logic
Output voltage up to +80V
Low power level shifting
32MHz equivalent data rate
Latched data outputs
Foreward and reverse shifting options (DIR pin)
Diode to V
Outputs may be hot switched
Note:
®
PP
Each SR (shift register) provides 16 outputs. SR1 supplies every fourth output starting with 1; SR2 supplies every fourth output with 2, etc.
technology
32MHz, 64-Channel Serial to Parallel Converter
allows effi cient power recovery
CLK
DIR
with Push-Pull Outputs
D 4
D 4
D 1
D 1
SR4
O
I
O
I
D 2
D 3
D 3 I
D 2
SR3
O
O
I
D 2
D 3
D 2 I
SR2
D 3
O
O
I
D 1
D 4
D 1 I
D 4
SR1
O
O
I
V
DD
LE
GND
BL
General Description
The device has 4 parallel 16-bit registers, permitting data
rates 4x the speed of one (they are clocked together). There
are also 64 latches and control logic to perform the polarity
select and blanking of the outputs. HVOUT1 is connected
to the fi rst stage of the fi rst shift register through the polarity
and blanking logic. Data is shifted through the shift registers
on the logic low to high transition of the clock. The DIR pin
causes CCW shifting when connected to GND, and CW
shifting when connected to VDD. A data output buffer is
provided for cascading devices. This output refl ects the
current status of the last bit of the shift register (HVOUT64).
Operation of the shift register is not affected by the LE (latch
enable), BL (blanking), or the POL (polarity) inputs. Transfer
of data from the shift registers to the latches occurs when
the LE input is high. The data in the latches is stored when
the LE is low.
POL
V
PP
HV
HV
HV
HV
HV
HV
HV
HV
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
10
11
12
61
62
63
64
1
5
9
•
•
•
2
6
•
•
•
3
7
•
•
•
4
8
•
•
•
HV57708

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HV57708_07 Summary of contents

Page 1

Serial to Parallel Converter Features ► HVCMOS ® technology ► 5.0V CMS Logic ► Output voltage up to +80V ► Low power level shifting ► 32MHz equivalent data rate ► Latched data outputs ► Foreward and reverse shifting ...

Page 2

Ordering Information Package Options Device 80-Lead PQFP HV57708 HV57708PG-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Supply voltage Output voltage , V PP Logic input levels (1) Ground current Continuous total power dissipation Operating ...

Page 3

DC Electrical Characteristics Symbol Parameter I V supply current High voltage supply current PP I Quiescent V supply current DDQ High level output Low level output High-level ...

Page 4

Input and Output Equivalent Circuits V DD Input GND Logic Inputs Switching Waveforms Data Input 50% Clock 50% Data Out Latch Enable HVOUT w/ S/R LOW HVOUT w/ S/R HIGH V DD Data Out GND Logic Data Output Data Valid ...

Page 5

Function Table Function Data CLK All O/P high X X All O/P low X X O/P normal X X O/P inverted _↑ Data falls _ H _↑ through _ (latches L _↑ transparent _↑ ...

Page 6

Pin Function Pin Pin Function # # 21 1 HVOUT24/ HVOUT23/ HVOUT22/ HVOUT21/ HVOUT20/ HVOUT29/ HVOUT18/ HVOUT17/ HVOUT16/ HVOUT15/ HVOUT14/51 ...

Page 7

PQFP Package Outline (PG) 20x14mm body, 0.80mm pitch E Note 1 E1 (Index Area D1/4 x E1/ Top View Note 1: A Pin 1 identifi er must be located in the index area indicated. ...

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