AT89S53-16AA ATMEL Corporation, AT89S53-16AA Datasheet
AT89S53-16AA
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AT89S53-16AA Summary of contents
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... SPI serial interface conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Downloadable Flash on a monolithic chip, the Atmel AT89S53 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89S53 provides the following standard features: 12K bytes of Downloadable ...
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... TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance inputs. Port 0 can also be configured to be the multiplexed low- order address/data bus during accesses to external pro- gram and data memory. In this mode, P0 has internal pul- lups. AT89S53 4-218 33 P0.4 (AD4) 32 P0.5 (AD5 ...
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Block Diagram V CC GND RAM ADDR. REGISTER B REGISTER PSEN TIMING ALE/PROG INSTRUCTION AND REGISTER CONTROL RST WATCH OSC P0.0 - P0.7 PORT 0 DRIVERS PORT 0 RAM LATCH ACC TMP2 TMP1 ALU INTERRUPT, SERIAL ...
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... Port 3 pins that are externally being pulled low will source current (I ) because of the pullups. IL Port 3 also serves the functions of various special features of the AT89S53, as shown in the following table. Port 3 also receives some control signals for Flash pro- gramming and verification. AT89S53 4-220 ...
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... XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Table 1. AT89S53 SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC 0E0H 00000000 0D8H PSW 0D0H 00000000 T2CON T2MOD 0C8H ...
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... Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. AT89S53 4-222 SPI Registers Control and status bits for the Serial Periph- eral Interface are contained in registers SPCR (shown in Table 4) and SPSR (shown in Table 5) ...
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Dual Data Pointer Registers To facilitate accessing exter- nal data memory, two banks of 16 bit Data Pointer Regis- ters are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR WCON selects ...
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... SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF bit) are cleared by reading the SPI status register with SPIF and WCOL set, and then accessing the SPI data register. AT89S53 4-224 ...
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... Bit 7 6 Data Memory - RAM The AT89S53 implements 256 bytes of RAM. The upper 128 bytes of RAM occupy a parallel space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. ...
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... Timer 0 and 1 Timer 0 and Timer 1 in the AT89S53 operate the same way as Timer 0 and Timer 1 in the AT89C51, AT89C52 and AT89C55. For further information, see the October 1995 Microcontroller Data Book, page 2-45, section titled, “Timer/Counters.” Timer 2 Timer bit Timer/Counter that can operate as either a timer or an event counter ...
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EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The over- flow also causes the timer registers to be reloaded with the 16 bit value in RCAP2H and ...
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... Figure 3. Timer 2 Auto Reload Mode (DCEN = 1) Figure 4. Timer 2 in Baud Rate Generator Mode NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 ÷ 2 OSC C/ C/ PIN TRANSITION DETECTOR T2EX PIN AT89S53 4-228 TH2 TL2 CONTROL TR2 RCAP2H RCAP2L EXF2 CONTROL EXEN2 TIMER 1 OVERFLOW ÷ ...
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Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the ...
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... SPI STATUS REGISTER AT89S53 4-230 UART The UART in the AT89S53 operates the same way as the UART in the AT89C51, AT89C52 and AT89C55. For fur- ther information, see the October 1995 Microcontroller Data Book, page 2-49, section titled, “Serial Interface.” Serial Peripheral Interface ...
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Writing to the SPI data register of the master CPU starts the SPI clock generator, and the data written shifts out of the MOSI pin ...
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... SS (TO SLAVE) *Not defined but normally LSB of previously transmitted character Interrupts The AT89S53 has a total of six interrupt vectors: two exter- nal interrupts (INT0 and INT1), three timer interrupts (Tim- ers 0, 1, and 2), and the serial port interrupt. These inter- rupts are all shown in Figure 10. ...
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Figure 11. Oscillator Connections Note: C1 for Crystals = for Ceramic Resonators Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively inverting amplifier that can be ...
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... Program Memory Lock Bits The AT89S53 has three lock bits that can be left unpro- grammed (U) or can be programmed (P) to obtain the addi- tional features listed in the following table. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow- ...
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... Turn V power off. CC DATA Polling The AT89S53 features DATA Polling to indicate the end of a write cycle. During a write cycle in the parallel or serial pro- gramming mode, an attempted read of the last byte written will result in the complement of the written datum on P0.7 (parallel mode), and on the MSB of the serial output byte on MISO (serial mode) ...
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... Serial Programming Algorithm To program and verify the AT89S53 in the serial program- ming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between V and GND pins. CC Set RST pin to “H” crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 24 MHz clock to XTAL1 pin and wait for at least 10 milliseconds ...
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Flash Parallel Programming Modes Mode Serial Prog. Modes Chip Erase Write (12K bytes) Memory Read (12K bytes) Memory Write Lock Bits: Bit - 1 Bit - 2 Bit - 3 Read Lock Bits: Bit - 1 Bit - 2 Bit ...
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... Figure 14. Flash Serial Downloading + PGM P0 DATA INSTRUCTION INPUT ALE PROG DATA OUTPUT CLOCK 3-24 Mhz RST PSEN + PGM DATA P0 (USE 10K PULLUPS) ALE RST I H PSEN +4.0V to 6.0V AT89S53 V CC P1.5/MOSI P1.6/MISO P1.7/SCK XTAL2 XTAL1 RST GND ...
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Flash Programming and Verification Characteristics - Parallel Mode T = 0°C to 70° 5.0V 10 Symbol Parameter V Programming Enable Voltage PP I Programming Enable Current PP 1/t Oscillator Frequency CLCL t Address Setup to PROG ...
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... Flash Programming and Verification Waveforms - Parallel Mode Serial Downloading Waveforms SERIAL CLOCK INPUT SCK/P1.7 SERIAL DATA INPUT MOSI/P1.5 SERIAL DATA OUTPUT MISO/P1.6 AT89S53 4-240 LSB MSB LSB MSB ...
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Absolute Maximum Ratings* Operating Temperature .................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage............................................. 6.6V DC Output Current...................................................... 15 Characteristics The values shown ...
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... Address Low AVWL t Data Valid to WR Transition QVWX t Data Valid to WR High QVWH t Data Hold After WR WHQX t RD Low to Address Float RLAZ High to ALE High WHLH AT89S53 4-242 12MHz Oscillator Variable Oscillator Min Max Min 0 127 CLCL CLCL 48 ...
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External Program Memory Read Cycle External Data Memory Read Cycle 4-243 ...
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... External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL AT89S53 4-244 V = 4.0V to 6.0V CC Min Max Units MHz ...
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Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for V Symbol Parameter t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock Rising QVXH Edge t Output Data Hold After ...
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... Notes: AT89S53 4-246 1. XTAL1 tied to GND for I (power down Lock bits programmed ...
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... Ordering Information Speed Power Ordering Code (MHz) Supply 16 4.0V to 6.0V AT89S53-16AA AT89S53-16JA AT89S53-16PA 24 4.0V to 6.0V AT89S53-24AC AT89S53-24JC AT89S53-24PC 4.0V to 6.0V AT89S53-24AI AT89S53-24JI AT89S53-24PI 33 4.5V to 5.5V AT89S53-33AC AT89S53-33JC AT89S53-33PC 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) ...
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... AT89S53 4-248 ...