LM9040M National Semiconductor, LM9040M Datasheet - Page 6

• Manufacturer Part Number: LM9040M
• Description: Dual Lambda Sensor Interface Amplifier
• Manufacturer: National Semiconductor

Common Mode Filtering
For a common mode sine wave signal having a frequency
100 Hz and with a F
mon mode rejection would be
If the common mode sine wave has a peak to peak value of
2V the maximum voltage error at the output would be
As this formula shows the value of V
to the frequency of the CMR signal If the frequency is dou-
bled the value of V
a small bypass capacitor (C
to ground will help counter this problem See Figure 6 How-
ever the use of this bypass capacitor creates a new prob-
lem in that the differential input is no longer balanced While
the Lambda sensor is cold (i e R
is little difference in CMR performance As the Lambda sen-
sor heats to the operating temperature and the sensor re-
sistance decreases the common mode signal is no longer
applied to both inputs equally This imbalance causes
V
inverting input will see the full common mode signal while
the non-inverting input will see an attenuated common
mode signal
The selection of the value of the CMR bypass capacitor
needs to be balanced with the need for reasonable reduc-
tion or elimination of common mode signals with both cold
and hot sensors Since normal operation will need to in-
clude consideration of the entire impedance range of the
sensor a trade off in overall application performance may
be needed
Generally the value of the CMR bypass capacitor should be
kept as low as possible and should not be larger than the
differential input filter capacitor Values in the range of
0 001
results but optimum results will need to be determined em-
pirically as the source of common mode signals will be
unique to each application
Gain and Filter Stage
The signal gain and filter stage is designed to have a DC
gain of 4 53 V V with a cut-off frequency of typically
500 Hz The external 4 k
series with the differential input impedance Together they
form a voltage divider circuit across the input such that the
net DC gain of the application circuit is 4 50 V V
OUT(CM)
F to 0 01
CMRR
to increase as R
V
OUT(CM)
CMRR
e
2 3 14159 100 5E-6 4 53
OUT(CM)
F will usually provide reasonable CMR
CLOCK
e
e
2V 0 014
0 014
resistors on each input pin are in
SENSOR
CM
is also doubled The addition of
of 100 kHz the minimum com-
) from the non-inverting input
e b
SENSOR l
decreases as the non-
OUT(CM)
e
37 dB
28 mV
(Continued)
10 Meg ) there
is proportional
6
The internal gain is set by the ratio of C
The corner frequency (
C
INT
and by F
FIGURE 8 Equivalent Gain and Filter Circuit
FIGURE 7 Simplified Gain and Filter Circuit
F
C
GAIN
e
CLOCK
2 3 14159 52 1E-12
DC
1E5 1 6383E-12
F
C
e
GAIN
b
e
7 4213 pF
1 6383 pF
3 dB) is set by the ratio of C
F
2
CLOCK
DC
e
C
C
C
FB
e
IN
C
INT
FB
4 53 V V
e
IN
and C
500 Hz
TL H 12372 – 17
TL H 12372 – 18
FB
FB
and