CLC109 National Semiconductor, CLC109 Datasheet - Page 3

• Manufacturer Part Number: CLC109
• Description: Low-Power/ Wideband/ Closed-Loop Buffer
• Manufacturer: National Semiconductor

PARAMETERS
FREQUENCY DOMAIN RESPONSE
TIME DOMAIN RESPONSE
DISTORTION AND NOISE RESPONSE
STATIC DC PERFORMANCE
MISCELLANEOUS PERFORMANCE
Operation
The CLC109 is a low-power, high-speed unity-gain buffer.
It uses a closed-loop topology which allows for accuracy
not usually found in high-speed buffers. A closed-loop
design provides high accuracy and low output impedance
through a wide bandwidth.
Single Supply Operation
Although the CLC109 is specified to operate from split
±5V power supplies, there is no internal ground reference
that prevents operation from a single voltage power
supply. For single supply operation the input signal should
be biased at a DC value of ½V
accomplished by AC coupling and rebiasing as shown in
the "Typical Application" illustrations on the front page.
The above electrical specifications provide typical
performance specifications for the CLC109 at 25°C while
operating from a single +3V or a single +5V power supply.
Printed Circuit Layout and Supply Bypassing
As with any high-frequency device, a good PCB layout is
required for optimum performance. This is especially
important for a device as fast as the CLC109.
To minimize capacitive feedthrough, pins 2, 3, 6, and 7
should be connected to the ground plane, as shown in
Figure 1. Input and output traces should be laid out as
transmission lines with the appropriate termination resistors
very near the CLC109. On a 0.065 inch epoxy PCB
material, a 50 transmission line (commonly called stripline)
can be constructed by using a trace width of 0.1" over a
complete ground plane.
Figure 1 shows recommended power supply bypassing.
Parasitic or load capacitance directly on the output of the
CLC109 will introduce additional phase shift in the device.
Electrical Characteristics
-3dB bandwidth
gain flatness
rise and fall time
overshoot
slew rate
2
3
small-signal gain
supply current
output voltage range
nd
rd
harmonic distortion
harmonic distortion
flatness
peaking
rolloff
CONDITIONS
V
V
V
DC to 30MHz
DC to 200MHz
DC to 60MHz
0.5V step
2.0V step
0.5V step
0.5V step
0.5V
1.0V
0.5V
1.0V
AC-coupled
R
R
R
out
out
out
L
L
L
=
=
=100
< 0.5V
< 2.0V
< 0.5V
pp
pp
pp
pp
,20MHz
,20MHz
,20MHz
,20MHz
CC
. This can be
pp
pp
pp
(V
CC
=+3V or V
V
CC
CC
13.9
0.89
0.75
3
-32
-29
1.5
1.1
30
35
= 3V
3
0
0
=+5V, -V
This phase shift can decrease phase margin and increase
frequency response peaking.
inserted between pin 6 and the capacitance effectively
decouples this effect. The graphs on the following page
illustrate the required resistor value and the resulting
performance vs. capacitance.
Precision buffed resistors (PRP8351 series from Precision
Resistive Products), which have low parasitic reactances,
were used to develop the data sheet specifications.
Precision carbon composition resistors or standard spirally-
trimmed RN55D metal film resistors will work, though they
may cause a slight degradation of ac performance due to
their reactive nature at high frequencies.
Evaluation Boards
Evaluation boards are available from National as part
CLC730012 (DIP) and CLC730045 (SOIC). This board
was used in the characterization of the device and provides
optimal performance. Designers are encouraged to copy
these printed circuit board layouts for their applications.
V
CC
Figure 1: Recommended circuit & evaluation
13.5
0.94
200
-37
-43
0.3
1.5
4.7
1.6
2.8
2.6
ee
90
35
= 5V
0
0
input impedance.
= 0V, T
R
for desired
in
is chosen
+5V
-5V
A
MHz
MHz
dB
dB
dB
ns
ns
%
V/ s
dBc
dBc
dBc
dBc
V/V
mA
V
V
UNITS
=+25°C, R
pp
pp
board schematic
V
6.8 F
6.8 F
in
C3
C4
+
+
R
in
desired output impedance.
L
4
= 100 , unless noted)
(CLC109 R
5
CLC109
R
1
A small series resistor
out
2
is chosen for
3
0.01 F
6 7
C1
C2
0.01 F
o
= 2.8 )
8
http://www.national.com
R
out
V
out