74AC163B STMicroelectronics, 74AC163B Datasheet

74AC163B

Manufacturer Part Number

74AC163B

Description

SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

Manufacturer

STMicroelectronics

Datasheet

1.74AC163B.pdf (7 pages)

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description

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

The ’AC16374 are 16-bit edge-triggered D-type

flip-flops

specifically for driving highly capacitive or

relatively

particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

The ’AC16374 can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock

(CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly.

OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

The 74AC16374 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and

functionality of standard small-outline packages in the same printed-circuit-board area.

The 54AC16374 is characterized for operation over the full military temperature range of –55 C to 125 C. The

74AC16374 is characterized for operation from –40 C to 85 C.

Members of the Texas Instruments

Widebus

3-State True Outputs

Full Parallel Access for Loading

Flow-Through Architecture Optimizes

PCB Layout

Distributed V

Minimizes High-Speed Switching Noise

EPIC

CMOS) 1- m Process

500-mA Typical Latch-Up Immunity at

125 C

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) Packages Using

25-mil Center-to-Center Pin Spacings and

380-mil Fine-Pitch Ceramic Flat (WD)

Packages Using 25-mil Center-to-Center

Pin Spacings

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

(Enhanced-Performance Implanted

low-impedance

with

Family

and GND Pin Configuration

3-state

outputs

loads.

POST OFFICE BOX 655303

They

designed

are

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS

DALLAS, TEXAS 75265

54AC16374 . . . WD PACKAGE

74AC16374 . . . DL PACKAGE

GND

1OE

2OE

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

1Q8

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

2Q8

SCAS123B – MARCH 1990 – REVISED APRIL 1996

(TOP VIEW)

WITH 3-STATE OUTPUTS

54AC16374, 74AC16374

1996, Texas Instruments Incorporated

1CLK

1D1

1D2

GND

1D3

1D4

1D5

1D6

GND

1D7

1D8

2D1

2D2

GND

2D3

2D4

2D5

2D6

GND

2D7

2D8

2CLK

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