24LC04 MicrochipTechnology, 24LC04 Datasheet - Page 5

• Manufacturer Part Number: 24LC04
• Description: 4K/8K2.5VI2CSerialEEPROMs
• Manufacturer: MicrochipTechnology

3.6
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code, for the 24LC04B/08B
this is set as 1010 binary for read and write operations.
The next three bits of the control byte are the block
select bits (B2, B1, B0). B2 is a don't care for both the
24LC04B and 24LC08B; B1 is a don't care for the
24LC04B. They are used by the master device to select
which of the two or four 256 word blocks of memory are
to be accessed. These bits are in effect the most sig-
nificant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24LC04B/08B moni-
tors the SDA bus checking the device type identifier
being transmitted, upon a 1010 code the slave device
outputs an acknowledge signal on the SDA line.
Depending on the state of the R/W bit, the 24LC04B/
08B will select a read or write operation.
FIGURE 3-2:
FIGURE 4-1:
FIGURE 4-2:
SDA LINE
Operation
BUS ACTIVITY
MASTER
BUS ACTIVITY
SDA LINE
BUS ACTIVITY
MASTER
1996 Microchip Technology Inc.
BUS ACTIVITY
Read
Write
X = Don’t care. B1 is don’t care for 24LC04B.
1
Device Addressing
START
0
Control
Code
1010
1010
SLAVE ADDRESS
CONTROL BYTE
ALLOCATION
BYTE WRITE
PAGE WRITE
1
S
S
T
A
R
T
S
S
T
A
R
T
0
Block Address
Block Address
Block Select
CONTROL
X
CONTROL
BYTE
This document was created with FrameMaker 4 0 4
READ/WRITE
BYTE
B1
R/W A
A
C
K
B0
ADDRESS (n)
WORD
R/W
A
C
K
1
0
A
C
K
ADDRESS
WORD
4.0
4.1
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24LC04B/08B. After
receiving another acknowledge signal from the
24LC04B/08B the master device will transmit the data
word to be written into the addressed memory location.
The 24LC04B/08B acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24LC04B/08B will
not generate acknowledge signals (Figure 4-1).
4.2
The write control byte, word address and the first data
byte are transmitted to the 24LC04B/08B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to 16 data bytes to
the 24LC04B/08B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
DATA n
WRITE OPERATION
Byte Write
Page Write
A
C
K
A
C
K
DATA n + 1
24LC04B/08B
DATA
A
C
K
DATA n + 15
DS21051E-page 5
A
C
K
P
S
T
O
P
A
C
K
S
T
O
P
P