93C46B-EP Microchip Technology, 93C46B-EP Datasheet - Page 3

• Manufacturer Part Number: 93C46B-EP
• Description: 1K 5.0V Microwire Serial EEPROM
• Manufacturer: Microchip Technology

2.0
2.1
A high level selects the device; a low level deselects the
device and forces it into standby mode. However, a pro-
gramming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be low for 250 ns minimum (T
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.2
The Serial Clock (CLK) is used to synchronize the com-
munication between a master device and the 93C46B.
Opcodes, addresses, and data bits are clocked in on
the positive edge of CLK. Data bits are also clocked out
on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
clock low time (T
freedom in preparing the opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but START condition has not been
detected, any number of clock cycles can be received
by the device, without changing its status (i.e., waiting
for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
TABLE 2-1
Instruction
1997 Microchip Technology Inc.
ERASE
WRITE
EWDS
EWEN
READ
WRAL
ERAL
PIN DESCRIPTION
Chip Select (CS)
Serial Clock (CLK)
CKL
SB
INSTRUCTION SET FOR 93C46B
1
1
1
1
1
1
1
). This gives the controlling master
Opcode
11
00
00
00
10
01
00
A5
A5
A5
1
0
1
0
CSL
A4
A4
A4
0
0
1
1
) between
CKH
Address
A3
A3
A3
X
X
X
X
) and
Preliminary
A2
A2
A2
X
X
X
X
A1
A1
A1
X
X
X
X
After detecting a START condition, the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcodes, addresses,
and data bits before an instruction is executed
(Table 2-1). CLK and DI then become don't care inputs
waiting for a new START condition to be detected.
2.3
Data In (DI) is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4
Data Out (DO) is used in the READ mode to output data
synchronously with the CLK input (T
tive edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (T
been initiated.
The status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the data line will be high
to indicate the device is ready.
A0
A0
A0
X
X
X
X
Note:
D15 - D0
D15 - D0
Data In
Data In (DI)
Data Out (DO)
—
—
—
—
—
CSL
CS must go low between consecutive
instructions.
) and an ERASE or WRITE operation has
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
Data Out
D15 - D0
HIGH-Z
HIGH-Z
93C46B
Req. CLK Cycles
PD
DS21172D-page 3
after the posi-
25
25
25
9
9
9
9