M24256-B STMicroelectronics, M24256-B Datasheet
M24256-B
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M24256-B Summary of contents
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... Year Data Retention (minimum) DESCRIPTION 2 These I C-compatible electrically erasable pro- grammable memory (EEPROM) devices are orga- nized as 32Kx8 bits (M24256-B) and 16Kx8 bits (M24128-B). These memory devices are compatible with the extended memory standard. This is a two wire serial interface that uses a bi-directional data bus and serial clock ...
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... M24256-B, M24128-B Figure 2A. PSDIP8 Connections M24256-B M24128 SCL SDA AI02810 Figure 2B. SO8 and TSSOP8 Connections M24256-B M24128 SCL SDA AI02811 Table 2. Absolute Maximum Ratings Symbol ...
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... A START condition must precede any data transfer command. The memory device con tinuously monitors (except during a programming ) for an I BUS V CC MASTER fc = 100kHz fc = 400kHz 100 1000 M24256-B, M24128 disable (WC protocol Bus SDA C BUS SCL C BUS ...
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... M24256-B, M24128-B 2 Figure Bus Protocol SCL SDA START CONDITION 1 SCL MSB SDA START CONDITION 1 SCL MSB SDA cycle) the SDA and SCL lines for a START condi- tion, and will not respond unless one is given. Stop Condition STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state ...
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... E2 E1 Table 4. Most Significant Byte b15 b14 b13 b12 Note: 1. b15 is treated as Don’t Care on the M24256-B series. b15 and b14 are Don’t Care on the M24128-B series. Table 5. Least Significant Byte sponds to each address byte with an acknowledge bit, and then waits for the data byte. ...
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... DATA IN N (cont’d) that is the most significant memory address bits (b14-b6 for the M24256-B and b13-b6 for the M24128-B) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. Data starts to become overwritten (in a way not formally specified in this data sheet) ...
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... For the Current Address Read mode, following a START condition, the master sends a Device Select Code with the RW bit set to ‘1’. The memory acknowl- edges this, and outputs the byte addressed by the M24256-B, M24128-B ACK ACK DATA IN 2 AI01106B ...
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... M24256-B, M24128-B Figure 7. Write Cycle Polling Flowchart using ACK NO First byte of instruction with already decoded by M24xxx NO ReSTART STOP internal address counter. The counter is then in- cremented. The master terminates the transfer with a STOP condition, as shown in Figure 8, with- out acknowledging the byte output. ...
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... ACK BYTE ADDR BYTE ADDR DEV SEL * ACK ACK ACK DATA OUT 1 DATA OUT N ACK ACK ACK BYTE ADDR BYTE ADDR DEV SEL * R/W NO ACK M24256-B, M24128-B ACK NO ACK DATA OUT R/W NO ACK ACK ACK DATA OUT 1 R/W AI01105C st th and 4 bytes) must be identical. 9/19 ...
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... M24256-B, M24128-B Table 7. DC Characteristics (T = – 4 2 – 1 Symbol Parameter Input Leakage Current I LI (SCL, SDA) I Output Leakage Current LO -W series: I Supply Current CC -R series: Supply Current -W series: I CC1 (Stand-by) -R series: V Input Low Voltage (SCL, SDA) ...
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... To avoid spurious STAR T and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 4. This is preliminary data. Table 10. AC Measurement Conditions Input Rise and Fall Times 0.2V Input Pulse Voltages Input and Output Timing 0.3V Reference Voltages M24256-B / M24128-B V =4 =2 =– =– ...
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... M24256-B, M24128-B Figure 10. AC Waveforms SCL SDA IN tCHDX START CONDITION SCL tCLQV SDA OUT SCL SDA IN tCHDH STOP CONDITION 12/19 tCHCL tCLCH tDLCL tDXCX tCLDX SDA SDA INPUT CHANGE tCLQX DATA VALID DATA OUTPUT tW tCHDX WRITE CYCLE tCHDH tDHDL STOP & BUS FREE ...
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... Table 11. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. – M24256-B, M24128-B Option T Tape and Reel Packing Temperature Range 6 – – Package BN PSDIP8 (0 ...
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... M24256-B, M24128-B Table 12. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame Symb. Typ 7. 2. Figure 11. PSDIP8 (BN Note: 1. Drawing is not to scale. 14/19 mm Min. Max. Typ. 3.90 5.90 0.49 – 3.30 5.30 0.36 0.56 1.15 1.65 0.20 0.36 9.20 9.90 – – 0.300 6.00 6.70 – – 0.100 7.80 – 10.00 3.00 3. ...
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... Note: 1. Drawing is not to scale. mm Min. Max. Typ. 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 – – 0.050 5.80 6.20 0.25 0.50 0. M24256-B, M24128-B inches Min. Max. 0.053 0.069 0.004 0.010 0.013 0.020 0.007 0.010 0.189 0.197 0.150 0.157 – – 0.228 0.244 0.010 0.020 0.016 0.035 0.004 C L 15/19 ...
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... M24256-B, M24128-B Table 14. TSSOP8 - 8 lead Thin Shrink Small Outline Symb. Typ 0. Figure 13. TSSOP8 (DW Note: 1. Drawing is not to scale. 16/19 mm Min. Max. Typ. 1.10 0.05 0.15 0.85 0.95 0.19 0.30 0.09 0.20 2.90 3.10 6.25 6.50 4.30 4.50 – – 0.026 0.50 0. 0.08 DIE inches Min. Max. 0.043 0.002 ...
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... Note: 1. Drawing is not to scale. mm Min. Max. Typ. 1.10 0.05 0.15 0.85 0.95 0.19 0.30 0.09 0.20 4.90 5.10 6.25 6.50 4.30 4.50 – – 0.026 0.50 0. 0.08 DIE M24256-B, M24128-B inches Min. Max. 0.043 0.002 0.006 0.033 0.037 0.007 0.012 0.004 0.008 0.193 0.197 0.246 0.256 0.169 0.177 – – 0.020 0.028 0.003 C L TSSOP 17/19 ...
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... M24256-B, M24128-B Table 16. Revision History Date 28-Dec-1999 TSSOP8 package added ( OrderingInfo, PackageMechData). E2, E1, E0 must be tied to Vcc or Vss, on page 3 24-Feb-2000 Low Pass Filter Time Constant changed to Glitch Filter in Table 8 18/19 Description of Revision ...
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... All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. 2000 STMicroelectronics - All Rights Reserved http:// www.st.com M24256-B, M24128-B 19/19 ...