LH28F016SCH-L Sharp Electrionic Components, LH28F016SCH-L Datasheet
LH28F016SCH-L
Related parts for LH28F016SCH-L
LH28F016SCH-L Summary of contents
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... TEMPERATURE LH28F016SC +70˚C LH28F016SCH-L –40 to +85˚C In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. ...
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PIN CONNECTIONS 40-PIN TSOP (Type CE RP# 12 ...
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BLOCK DIAGRAM Y DECODER INPUT BUFFER ADDRESS LATCH X DECODER ADDRESS COUNTER DQ - OUTPUT INPUT BUFFER BUFFER IDENTIFIER REGISTER STATUS REGISTER DATA COMPARATOR Y GATING 32 64 k-BYTE BLOCKS - 3 - LH28F016SC-L/SCH-L ...
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... INPUT 0 20 are internally latched during a write cycle. DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs data during memory array, status register, and identifier code read cycles. Data pins INPUT float to high-impedance when the chip is deselected or outputs are disabled. Data is OUTPUT internally latched during a write cycle ...
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... The LH28F016SC-L/SCH-L are high-performance 16 M-bit SmartVoltage flash memories organized as 2 M-byte of 8 bits. The 2 M-byte of data is arranged in thirty-two 64 k-byte blocks which are individually erasable, lockable, and unlockable in- system. The memory map is shown in Fig. 1. SmartVoltage technology provides a choice of V and V combinations, as shown in Table meet system performance and power expectations ...
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... The access time voltage range of 4.75 to 5.25 V over the temperature range +70°C (LH28F016SC-L)/ –40 to +85°C (LH28F016SCH-L). At 4 the access time is 100 ns or 120 ns. At lower CC V voltage, the access time is 120 ns or 150 ...
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... After initial device power-up or return from deep power-down mode (see Table 2 "Bus Operations"), 24 the device defaults to read array mode. Manipulation 23 of external memory control pins allow array read, 22 standby, and output disable operations. 21 Status register and identifier codes can be 20 accessed through the CUI independent of the V 19 voltage ...
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... BUS OPERATION The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, or status register independent of the V voltage ...
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... Automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input ...
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... Lock) or block within the device (Block Lock locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory MODE NOTE Read ...
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... X = Any valid address within the device Identifier code address : see Fig Address within the block being erased or locked Address of memory location to be written. 3. SRD = Data read from status register. See Table 6 for a description of the status register bits Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first) ...
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... Device is Locked • Reserved for Future Use NOTE : 1. X selects the specific block lock configuration code to be read. See Fig. 2 for the device identifier code memory map. 4.3 Read Status Register Command The status register may be read to determine when a block erase, byte write, or lock-bit configuration is complete and whether the operation completed successfully ...
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... Block Erase Suspend Command The Block Erase Suspend command allows block . If erase interruption to read or byte write data in HH another block of memory. Once the block erase , SR.1 and SR.5 process starts, writing the Block Erase Suspend IH < command requests that the WSM suspend the ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear ...
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When the set lock-bit operation is complete, status register bit SR.4 should be checked error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. ...
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MASTER BLOCK OPERATION LOCK-BIT LOCK-BIT 0 Block Erase X or Byte Write Set Block Lock-Bit 1 X Set Master X X Lock-Bit 0 X Clear Block Lock-Bits 1 X WSMS ESS ECLBS SR.7 = ...
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Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No Erase Loop 0 Suspend SR.7 = Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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Start Write 40H, Address Write Byte Data and Address Read Status Register Suspend Byte No Write Loop 0 Suspend SR.7 = Byte Write Yes 1 Full Status Check if Desired Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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Start Write B0H Read Status Register 0 SR Block Erase SR.6 = Completed 1 Read Read Byte Write or Byte Write? Read Array Data Byte Write Loop No Done? Yes Write D0H Write FFH Block Erase Resumed ...
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Start Write B0H Read Status Register 0 SR Byte Write SR.2 = Completed 1 Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read Byte Write Resumed Array Data Fig. 6 Byte Write ...
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Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error ...
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Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error ...
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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for : a. Lowest possible memory power consumption. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’ ...
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... When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during or CE# PP system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed. . LKO ...
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... LH28F016SC-L During Read, Block Erase, Byte Write and Lock-Bit Configuration ........ 0 to +70°C Temperature under Bias ............. –10 to +80°C • LH28F016SCH-L During Read, Block Erase, Byte Write and Lock-Bit Configuration .... –40 to +85°C Temperature under Bias ............. –40 to +85°C Storage Temperature ........................ –65 to +125°C Voltage On Any Pin , and RP#) .... – ...
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CAPACITANCE SYMBOL PARAMETER C Input Capacitance IN C Output Capacitance OUT NOTE : 1. Sampled, not 100% tested. 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7 V for a Logic ...
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... UNDER TEST Includes Jig L Capacitance Fig. 12 Transient Equivalent Testing Load Circuit Test Configuration Capacitance Loading Value TEST CONFIGURATION V = 3.3±0.3 V, 2 (NOTE 5.0±0. 5.0±0 NOTE : 1. Applied to high-speed products, LH28F016SC-L95 and LH28F016SCH-L95. OUT - 27 - LH28F016SC-L/SCH-L C (pF 100 ...
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DC CHARACTERISTICS SYMBOL PARAMETER NOTE I Input Load Current LI I Output Leakage Current Standby Current CCS CC LH28F016 V Deep Power- SC CCD Down Current LH28F016 SCH Read ...
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DC CHARACTERISTICS (contd.) SYMBOL PARAMETER NOTE Input Low Voltage Input High Voltage IH V Output Low Voltage Output High Voltage OH1 (TTL) Output High Voltage OH2 (CMOS) ...
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... LH28F016SC-L/SCH-L (NOTE 1) LH28F016SC-L12 LH28F016SCH-L12 UNIT MAX. MIN. MAX. 170 150 170 150 170 600 600 LH28F016SC-L12 LH28F016SCH-L12 UNIT MAX. MIN. MAX. 150 120 150 120 150 600 600 ELQV ...
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... See Fig. 11 "Transient Input/Output Reference Waveform" and Fig. 12 "Transient Equivalent Testing after the falling Load Circuit" (Standard Configuration) for testing GLQV . characteristics LH28F016SC-L/SCH-L (NOTE 1) (NOTE 5) (NOTE 5) LH28F016SC-L95 LH28F016SC-L12 LH28F016SCH-L95 LH28F016SCH-L12 MIN. MAX. MIN. MAX. 100 120 100 120 100 120 400 400 45 50 ...
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Standby V IH ADDRESSES ( CE# ( OE# ( WE# ( High Z DATA (D/Q) ( ...
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... LH28F016SC-L/SCH-L LH28F016SC-L12 LH28F016SCH-L12 UNIT MAX. MIN. MAX. 170 ns 1 µ LH28F016SC-L12 LH28F016SCH-L12 UNIT MAX. MIN. MAX. 150 ns 1 µ 100 ns 100 100 100 ...
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... See Fig. 11 "Transient Input/Output Reference for block erase, Waveform" and Fig. 12 "Transient Equivalent Testing IN Load Circuit" (Standard Configuration) for testing characteristics LH28F016SC-L/SCH-L (NOTE 1) (NOTE 6) (NOTE 6) LH28F016SC-L95 LH28F016SC-L12 LH28F016SCH-L95 LH28F016SCH-L12 MIN. MAX. MIN. MAX. 100 120 100 100 ...
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V IH ADDRESSES ( CE# ( ELWL V IH OE# ( WE# ( High DATA (D/Q) t PHWL V IL ...
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... LH28F016SC-L/SCH-L LH28F016SC-L12 LH28F016SCH-L12 UNIT MIN. MAX. 170 ns 1 µ LH28F016SC-L12 LH28F016SCH-L12 UNIT MIN. MAX. 150 ns 1 µ 100 ns 100 100 ns 0 ...
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... See Fig. 11 "Transient Input/Output Reference for block erase, Waveform" and Fig. 12 "Transient Equivalent Testing IN Load Circuit" (Standard Configuration) for testing characteristics LH28F016SC-L/SCH-L (NOTE 1) (NOTE 6) (NOTE 6) LH28F016SC-L95 LH28F016SC-L12 LH28F016SCH-L95 LH28F016SCH-L12 MIN. MAX. MIN. MAX. 100 120 100 100 ...
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V IH ADDRESSES ( AVAV V IH WE# ( WLEL V IH OE# ( CE# ( High DATA (D/Q) t ...
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RESET OPERATIONS V OH RY/BY# ( RP# ( RY/BY# ( RP# ( 2.7 V/3.3 V RP# (P) V ...
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BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE • 3.3±0 +70˚C or – SYMBOL PARAMETER NOTE t WHQV1 Byte Write Time t EHQV1 Block Write Time t WHQV2 ...
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ORDERING INFORMATION Product line designator for all SHARP Flash products ( Device Density 016 = 16 M-bit Architecture S = Symmetrical Block Power Supply ...
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TSOP (TSOP040-P-1020 0.3 20.0 0.2 18.4 0.3 19.0 PACKAGING Package base plane ...
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SOP (SOP044-P-0600 0.4 0 0.1 0.15 M 1.27 TYP 0.2 28.2 PACKAGING 0.15 0.05 Package base plane ...
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CSP (FBGA048-P-0810 0.1 S 3.0 0.8 0 0.1 S TYP. 0.4 + 0.2 10 TYP. TYP. TYP 0.03 0. PACKAGING Land ...