DSM2190F4 STMicroelectronics, DSM2190F4 Datasheet
DSM2190F4
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DSM2190F4 Summary of contents
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... Programmable Security Bit blocks access of de- vice programmers and readers Zero-Power Technology – As low standby current Packaging software...Free – 52-pin PQFP or 52-pin PLCC Flash Memory Speed, Endurance, Retention +85 C – 150 ns, 100K cycles, 15 year retention DSM2190F4V PQFP52 (T) PLCC52 (K) TM cable with PC 1/61 ...
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... DSM2190F4 TABLE OF CONTENTS Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DSP Address/Data/Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Main Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Secondary Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Programmable Logic (PLDs Runtime Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 JTAG ISP Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Security and NVM Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typical Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Specifying the Memory Map with PSDsoft ExpressTM ...
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... Table: Flash Memory Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table: Reset (Reset) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table: ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table: PLCC52 - 52 lead Plastic Leaded Chip Carrier, rectangular . . . . . . . . . . . . . . . . . . . . . . . . 55 Table: Assignments – PLCC52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table: PQFP52 - 52 lead Plastic Quad Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table: Pin Assignments – PQFP52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table: Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 DSM2190F4 3/61 ...
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... DSM2190F4 SUMMARY DESCRIPTION The DSM2190F4 is a system memory device for use with the Analog Devices ADSP-2191 DSP. DSM means Digital signal processor System Memory. A DSM device brings In-System Pro- grammable (ISP) Flash memory, parameter stor- age, programmable logic, and additional I/O to DSP systems. The result is a simple and flexible two-chip solution for DSP designs ...
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... Table 1. DSM2190F4V DSP Memory System Devices Main Flash Part Number Memory 256KBytes = ...
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... DSP address lines can be de- coded as well as DSP memory strobes; , and . There are many different ways the IOMS MSx DSM2190F4 can be configured and used depend- ing on system requirements. One convenient way is to combine the function of the the signal. Doing this allows the DSP core to BMS ...
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... This 8-bit register can be loaded and read by the DSP at runtime as one of the csiop registers. Its outputs feed directly into the PLDs. The page reg- ister can be used for special memory mapping re- quirements and also for general logic. DSM2190F4 DSM2190F4 DSP SYSTEM MEMORY A ALLO- B ...
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... DSM2190F4 I/O Ports The DSM has 19 individually configurable I/O pins distributed over the three ports (Ports B, C, and D). Each I/O pin can be individually configured for dif- ferent functions such as standard MCU I/O ports or PLD I pin by pin basis. (MCU I/O means that for each pin, its output state can be controlled ...
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... Figure 6 Note 2: Port D pin PD1 (or any PLD input pin) can be connected to the DSP A17 output. See Figure 6. Note 3: Port D pin PD2 (or any PLD input pin) can be connected to the DSP A18 output. See Figure 6 V Supply Voltage CC GND Ground pins Description DSM2190F4 9/61 ...
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... DSM2190F4 TYPICAL CONNECTIONS Figure 6 shows a typical connection scheme. Many connection possibilities exist since many DSM pins are multipurpose. This scheme illus- trates the use of a combined function (functions as and ), and many I/O pins. It BMS MSx also illustrates how to chain the DSM and DSP de- vices together on the JTAG bus ...
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... Figure 6. Typical Connections CONNECTOR JTAG DSM ohm 10k DSM2190F4 CONNECTOR JTAG DSP 11/61 ...
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... DSM2190F4 TYPICAL MEMORY MAP There many different ways to place (or map) the addresses of DSM memory and I/O depending on system requirements. The DPLD allows complete mapping flexibility. Figure 7 shows one possible system memory map. In this case, the DSP will bootload (via DMA) the contents of Main Flash memory upon reset ...
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... Main Flash 28000 27FFF 32K bytes Main Flash 20000 1FFFF 32K bytes Main Flash 18000 17FFF 32K bytes Main Flash 10000 fs7 fs6 fs5 fs4 fs3 fs2 fs1 fs0 DSM2190F4 DSP I/O Memory Space (IOMS) csiop 02000-020FF 256 CONTROL REGS AI04962 13/61 ...
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... DSM2190F4 SPECIFYING THE MEMORY MAP WITH PSDSOFT EXPRESS The memory map shown in Figure 7 can be easily implemented using PSDsoft Express and-click environment. PSDsoft Express generate Hardware Definition Language (HDL) Figure 8. HDL Statements Generated from PSDsoft Express to Implement Memory Map csiop = ((address >= ^h2000) & (address <= ^h20FF) & (!_ioms)); ...
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... Also read to determine Secondary Flash Protection Setting status. No Writes. Write to enable JTAG Pins (optional feature). Read to C7 check status. B0 Power Management Register 0. Write and read. B4 Power Management Register 2. Write and read. E0 Memory Page Register. Write and read. DSM2190F4 strobe. These registers are accesses in Description 15/61 ...
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... DSM2190F4 DETAILED OPERATION Figure 5 shows major functional areas of the de- vice: Flash Memories PLDs (DPLD, CPLD, Page Register) DSP Bus Interface (Address, Data, Control) I/O Ports Runtime Control Registers JTAG ISP Interface The following describes these functions in more detail. Flash Memories The Main Flash memory array is divided into eight equal 32K byte sectors ...
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... Write 55h Write 80h Write AAh to to XXAAAh to XX555h XX555h Write 55h Write 80h Write AAh to to XXAAAh to XX555h XX555h DSM2190F4 Cycle 5 Cycle 6 Cycle 7 Write 55h Write 10h to XXAAAh to XX555h Write 30h Write 30h Write 55h to another to another to XXAAAh ...
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... DSM2190F4 Instruction Sequences An instruction sequence consists of a sequence of specific write or read operations. Each byte written to the device is received and sequentially decoded and not executed as a standard write operation to the memory array. The instruction sequence is ex- ecuted when the correct number of bytes are prop- ...
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... Table 5). Once the DSP issues a Flash memory Program or Erase instruction sequence, it must check for the status bits for completion. The embedded algo- rithms that are invoked inside the device provide several ways give status to the DSP. Status may DSM2190F4 19/61 ...
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... DSM2190F4 be checked using any of three methods: Data Poll- ing, Data Toggle, or Ready/Busy (pin PC3). Data Polling. Polling on the Data Polling Flag (DQ7) bit is a method of checking whether a Pro- gram or Erase cycle is in progress or has complet- ed. Figure 10 shows the Data Polling algorithm. ...
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... During a Sector Erase, the memory status may be checked by reading the Error Flag (DQ5) bit, the Toggle Flag (DQ6) bit, and the Data Polling Flag (DQ7) bit, as detailed in the section entitled “Pro- gramming Flash Memory”, on page 19. DSM2190F4 21/61 ...
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... DSM2190F4 During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend Sector Erase instruction sequences. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed. The address provided with the initial Flash Sector ...
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... Note: 1. DSP address lines A16, A17, and others may enter the DSM device on any pin on ports See Figure 6 for recommended connections. 2. Additional DSP control signals may enter the DMS device on any pin on Ports See Figure 6 for recom- mended connections. DSM2190F4 INTERNAL SELECTS AND LOGIC DPLD AND ...
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... DSM2190F4 The DPLD performs address decoding, and gen- erates select signals for internal and external com- ponents, such as memory, registers, and I/O ports. The DPLD can generates External Chip Select (ECS0-ECS2) signals on Port D. The CPLD can be used for logic functions, such as loadable counters and shift registers, state ma- chines, and encoding and decoding logic ...
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... JTAG Select signal (enables JTAG operations on Port C when multiplexing JTAG signals with general I/O signals) 3 external chip select output signals for Port D pins, each with one product term. (16) (8) (8) (8) (16) (3) (3) (1) (1) DSM2190F4 3 CSBOOT0 3 4 Secondary CSBOOT1 Flash Memory Sector Selects 3 CSBOOT2 3 CSBOOT3 3 FS0 ...
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... DSM2190F4 COMPLEX PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. See application note AN1171 for details on how to specify logic us- ing PSDsoft Express. As shown in Figure 15, the CPLD has the following ...
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... TM , but McellBC0-McellBC3 all have four native product terms and may borrow up to five more McellBC4-McellBC7 all have four native product terms and may borrow up to six more. DSM2190F4 PORT B PINS PORT C PINS ...
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... DSM2190F4 Each Macrocell may only borrow product terms from certain other Macrocells. Product terms al- ready in use by one Macrocell are not available for another Macrocell. Product term allocation does not add any propagation delay to the logic equation requires more product terms than are available to it through product term allocation, then “ ...
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... CPLD. Each product term output is used to latch or clock four IMCs. Port inputs 3-0 can be controlled by one product term and 7-4 by another. Configurations for the IMCs are specified by equa- tions specified in PSDsoft Express. See Applica- tion note AN1171 . DSM2190F4 DIRECTION REGISTER Port Driver PT Input Macrocell ...
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... DSM2190F4 DSP Bus Interface The “no-glue logic” DSP Bus Interface allows di- rect connection. DSP address, data, and control signals connect directly to the DSM device. See Figure 6 for typical connections. DSP address, data and control signals are routed to Flash memory, I/O control ( csiop ), OMCs, and IMCs within the DMS ...
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... DSP through normal read/write bus cycles of the csiop registers listed in Table 4. The pins of a port are individually configurable and each bit in the register controls its respective pin. For example, Bit register refers to Bit 0 of its DSM2190F4 TM , and Port D Yes No ...
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... DSM2190F4 port. The three Port Configuration Registers (PCR), are shown in Table 12. Default is logic 0. Table 12. Port Configuration Registers (PCR) Register Name Port Data In B,C,D Data Out B,C,D Direction B,C,D 1 B,C,D Drive Select Note: 1. See Table 16 for Drive Register bit definition. Data In Register. The DSP may read the Data In registers in the csiop block at any time to deter- mine the logic state of a Port pin ...
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... DATA OUT DATA CPLD Input – Via the Input Macrocells (IMC). Open Drain/Slew Rate – pins PB3-PB0 can be configured to fast slew rate, pins PB7-PB4 can be configured to Open Drain Mode. DSM2190F4 Bit 3 Bit 2 Bit 1 Slew Slew Rate Rate Open Open Drain ...
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... DSM2190F4 Figure 21. Port C Structure DATA OUT REG MCELLBC [ 7:0 ] READ MUX DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD - INPUT Port C – Functionality and Structure Port C can be configured to perform one or more of the following functions (see Figure 21): MCU I/O Mode CPLD Output – McellBC7-McellBC0 outputs can be connected to Port B or Port C. CPLD Input – ...
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... Direction Register. (See Figure 23.) External Chip Selects for Port D pins do not consume OMCs. External chip select outputs can also come from the CPLD if chip se- lect equations are specified in PSDsoft Express for Ports DSM2190F4 PORT D PIN ENABLE PRODUCT TERM (.OE) AI02889 35/61 ...
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... DSM2190F4 Figure 23. Port D External Chip Select Signals 36/61 ENABLE (.OE) PT0 POLARITY BIT ENABLE (.OE) PT1 POLARITY BIT ENABLE (.OE) PT2 POLARITY BIT DIRECTION REGISTER PD0 PIN ECS0 DIRECTION REGISTER PD1 PIN ECS1 DIRECTION REGISTER PD2 PIN ECS2 AI02890 ...
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... Not used, and should be set to zero. Not used, and should be set to zero. CLKIN (PD1) input to the PLD AND Array is passed onto PLDs. Every change of CLKIN (PD1) Powers-up the PLD when Turbo bit is 0. Not used, and should be set to zero. Not used, and should be set to zero. DSM2190F4 37/61 ...
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... DSM2190F4 PLD Power Management The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0. By setting the bit to 1, the Turbo mode is off and the PLDs consume the specified stand-by current when the inputs are not switching for an extended time (100 ns for 3 ...
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... Configuration bits are OPR loaded. This loading of the device is completed typically long before the V ing level. Once the PLD is active, the state of the outputs are determined by the PSDsoft Express equations. DSM2190F4 t NLNH t NLNH-A t OPR Warm Reset , CNTL0) High CNTL0) ...
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... DSM2190F4 PROGRAMMING IN-CIRCUIT USING JTAG ISP In-System Programming (ISP) can be performed through the JTAG signals on Port C. This serial in- terface allows programming of the entire DSM de- vice or subsections (i.e. only Flash memory but not the PLDs) without and participation of the DSP. A blank DSM device soldered to a circuit board can be completely programmed seconds. The basic JTAG signals ...
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... DSM2190F4V devices and a wired- OR connection of TERR signals from those same devices. This is useful when several devices are “chained” together in a JTAG environment. PSD- soft Express puts TSTAT and TERR signals to open-drain by default. Click on 'Properties' in the JTAG-ISP window of PSDsoft Express to change to standard CMOS push-pull ...
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... DSM2190F4 AC/DC PARAMETERS These tables describe the AC and DC parameters of the device: DC Electrical Specification AC Timing Specification PLD Timing – Combinatorial Timing – Synchronous Clock Mode – Asynchronous Clock Mode – Input Macrocell Timing DSP Timing – Read Timing – Write Timing – Reset Timing ...
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... Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 1 or Hi- R2=500 ) DSM2190F4 Min. Max. Unit –65 125 °C 235 °C –0.6 7.0 V –0.6 7 ...
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... DSM2190F4 DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests performed under the Measure- Table 22. Operating Conditions Symbol V Supply Voltage ...
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... No Longer a Valid Logic Level Z Float PW Pulse Width INPUTS OUTPUTS STEADY INPUT STEADY OUTPUT MAY CHANGE FROM WILL BE CHANGING FROM MAY CHANGE FROM WILL BE CHANGING DON'T CARE CHANGING, STATE UNKNOWN OUTPUTS ONLY CENTER LINE IS TRI-STATE AI03102 DSM2190F4 45/61 ...
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... DSM2190F4 Table 26. DC Characteristics Symbol Parameter V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage (Note IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis HYS V (min) for Flash Erase and CC V LKO Program ...
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... ARPW Preset Pulse Width t CPLD Array Delay ARD Note: 1. Fast Slew Rate output available on PB3-PB0, and PD2-PD0. -15 Conditions Min Max Any Macrocell 29 DSM2190F4 Slew PT Turbo Unit 1 Aloc Off Rate Add 4 Add 20 Sub 6 ns Add 20 Sub 6 ns Add 20 Sub 6 ns ...
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... DSM2190F4 Table 28. CPLD Macrocell Synchronous Clock Mode Timing Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAX Internal Feedback (f CNT Maximum Frequency Pipelined Data t Input Setup Time S t Input Hold Time H t Clock High Time CH t Clock Low Time CL t Clock to Output Delay ...
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... Figure 31. Synchronous Clock Mode Timing – PLD CLKIN INPUT REGISTERED OUTPUT Figure 32. Asynchronous Clock Mode Timing (product term clock) CLOCK INPUT REGISTERED OUTPUT tER tEA tARPW tARP tCHA tCLA tSA tHA tCOA DSM2190F4 AI02863 AI02864 AI02859 49/61 ...
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... DSM2190F4 Table 30. Input Macrocell Timing Symbol Parameter t Input Setup Time IS t Input Hold Time IH t NIB Input High Time INH t NIB Input Low Time INL t NIB Input to Combinatorial Delay INO Note: 1. Inputs from Port B, and C relative to register/latch clock from the PLD. ...
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... Note: 1. Any input used to select an internal DSM function. Figure 34. Read Timing ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD Conditions Min 1 (Note ) AVQV ADDRESS VALID DATA VALID t SLQV t RLQV t RHQX t RLRH DSM2190F4 -15 Turbo Unit Off Max 150 Add 20 ns 150 tRHQZ AI04908 51/61 ...
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... DSM2190F4 Table 32. Write Timing Symbol Parameter t Address Valid to Leading Edge of WR AVWL t CS Valid to Leading Edge of WR SLWL t WR Data Setup Time DVWH t WR Data Hold Time WHDX t WR Pulse Width WLWH t Trailing Edge Address Invalid WHAX1 t Trailing Edge DPLD Address Invalid ...
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... Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in Read mode. Figure 36. Reset (RESET) Timing V (min NLNH-PO Power-On Reset RESET Parameter 2 Conditions 1 t OPR DSM2190F4 Min. Typ. Max 2.2 14 1200 100,000 100 30 Min ...
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... DSM2190F4 Table 35. ISC Timing Symbol t Clock (TCK, PC1) Frequency (except for PLD) ISCCF t Clock (TCK, PC1) High Time (except for PLD) ISCCH t Clock (TCK, PC1) Low Time (except for PLD) ISCCL t Clock (TCK, PC1) Frequency (PLD only) ISCCFP t Clock (TCK, PC1) High Time (PLD only) ...
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... Min. Max. 4.19 4.57 2.54 2.79 – 0.91 0.33 0.53 0.66 0.81 0.246 0.261 19.94 20.19 19.05 19.15 17.53 18.54 19.94 20.19 19.05 19.15 17.53 18.54 – – – – DSM2190F4 D2/E2 D3/ inches Typ. Min. 0.165 0.100 – 0.013 0.026 0.0097 0.785 0.750 0.690 0.785 0.750 0.690 0.050 – 0.035 – Max. 0.180 0.110 0.036 ...
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... DSM2190F4 Table 36. Assignments – PLCC52 Pin No. Pin Assignments 1 GND 2 PB5 3 PB4 4 PB3 5 PB2 6 PB1 7 PB0 8 PD2 9 PD1 10 PD0 11 PC7 12 PC6 13 PC5 14 PC4 GND 17 PC3 18 PC2 (VSTBY) 19 PC1 20 PC0 21 PA7 22 PA6 23 PA5 24 PA4 25 PA3 26 GND 56/61 CC Pin No. Pin Assignments 27 PA2 28 PA1 29 PA0 ...
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... Max. 2.35 0.25 1.80 2.10 0.22 0.38 0.11 0.23 12.95 13.45 9.90 10.10 – – 12.95 13.45 9.90 10.10 – – – – 0.73 1.03 – – 0° 7° 0.10 DSM2190F4 inches Typ. Min. 0.079 0.077 0.009 0.004 0.520 0.510 0.394 0.390 0.307 – 0.520 0.510 0.394 0.390 0.307 – 0.026 0.035 0.029 0.063 0° ...
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... DSM2190F4 Table 37. Pin Assignments – PQFP52 Pin No. Pin Assignments 1 PD2 2 PD1 3 PD0 4 PC7 5 PC6 6 PC5 7 PC4 GND 10 PC3 11 PC2 12 PC1 13 PC0 14 PA7 15 PA6 16 PA5 17 PA4 18 PA3 19 GND 20 PA2 21 PA1 22 PA0 23 AD0 24 AD1 25 AD2 26 AD3 58/61 CC Pin No. Pin Assignments 27 AD4 28 AD5 29 AD6 ...
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... Operating Voltage (Vcc 3.3V ± 10% Access Time 15 = 150 ns Package K = 52-pin PLCC T = 52-pin PQFP Temperature Range – (Industrial) For a list of available options (speed, package, etc.) or for further information on any aspect of this DSM21 device, please contact your nearest ST Sales Of- fice. DSM2190F4 59/61 ...
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... DSM2190F4 REVISION HISTORY Table 39. Document Revision History Date Rev. 27-Aug-2001 1.0 Document written 06-Nov-2001 1.1 Document released 17-Dec-2001 1.2 PQFP52 package mechanical data updated 18-Sep-2002 1.3 JTAG Debug bus separated from JTAG ISP bus 60/61 Description of Revision ...
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... India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies www.st.com DSM2190F4 61/61 ...