LM5100 National Semiconductor, LM5100 Datasheet - Page 9

• Manufacturer Part Number: LM5100
• Description: High Voltage High Side and Low Side Gate Driver
• Manufacturer: National Semiconductor

Timing Diagram
Layout Considerations
The optimum performance of high and low side gate drivers
cannot be achieved without taking due considerations during
circuit board layout. Following points are emphasized.
1. A low ESR / ESL capacitor must be connected close to
2. To prevent large voltage transients at the drain of the top
3. In order to avoid large negative transients on the switch
4. Grounging Considerations:
Power Dissipation Considerations
The total IC power dissipation is the sum of the gate driver
losses and the bootstrap diode losses. The gate driver
the IC, and between V
and HS pins to support high peak currents being drawn
from VDD during turn-on of the external MOSFET.
MOSFET, a low ESR electrolytic capacitor must be con-
nected between MOSFET drain and ground (V
node (HS) pin, the parasitic inductances in the source of
top MOSFET and in the drain of the bottom MOSFET
(synchronous rectifier) must be minimized.
is to confine the high peak currents from charging and
discharging the MOSFET gate in a minimal physical
area. This will decrease the loop inductance and mini-
mize noise issues on the gate terminal of the MOSFET.
The MOSFETs should be placed as close as possible to
the gate driver.
strap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low side MOSFET
body diode. The bootstrap capacitor is recharged on the
cycle-by-cycle basis through the bootstrap diode from
the ground referenced V
charging occurs in a short time interval and involves high
peak current. Minimizing this loop length and area on the
circuit board is important to ensure reliable operation.
a) The first priority in designing grounding connections
b) The second high current path includes the boot-
DD
and V
DD
bypass capacitor. The re-
SS
pins and between HB
SS
).
FIGURE 3.
9
losses are related to the switching frequency (f), output load
capacitance on LO and HO (C
and can be roughly calculated as:
There are some additional losses in the gate drivers due to
the internal CMOS stages used to buffer the LO and HO
outputs. The following plot shows the measured gate driver
power dissipation versus frequency and load capacitance. At
higher frequencies and load capacitance values, the power
dissipation is dominated by the power losses driving the
output loads and agrees well with the above equation. This
plot can be used to approximate the power losses due to the
gate drivers.
Gate Driver Power Dissipation (LO + HO)
V
CC
= 12V, Neglecting Diode Losses
P
DGATES
= 2 • f • C
L
), and supply voltage (V
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L
• V
DD
2
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DD
)