HIP6012 Intersil Corporation, HIP6012 Datasheet - Page 9

• Manufacturer Part Number: HIP6012
• Description: Buck and Synchronous-Rectifier Pulse-Width Modulator (PWM) Controller
• Manufacturer: Intersil Corporation

These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). Only the
upper MOSFET has switching losses, since the Schottky
rectifier clamps the switching node before the synchronous
rectifier turns on.
P
Where: D is the duty cycle = V
These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverse-
recovery of the lower MOSFETs body diode. The
gate-charge losses are dissipated by the HIP6012 and don't
heat the MOSFETs. However, large gate-charge increases
the switching interval, t
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
Standard-gate MOSFETs are normally recommended for
use with the HIP6012. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
less the boot diode drop (V
turns on. A logic-level MOSFET can only be used for Q1 if
the MOSFETs absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V
logic-level MOSFET can be used if its absolute gate-to-
source voltage rating exceeds the maximum voltage applied
to PVCC.
Figure 10 shows the upper gate drive supplied by a direct
connection to V
converter systems where the main input voltage is +5 VDC
or less. The peak upper gate-to-source voltage is
approximately VCC less the input supply. For +5V main
power and +12 VDC for the bias, the gate-to-source voltage
of Q1 is 7V. A logic-level MOSFET is a good choice for Q1
and a logic-level MOSFET can be used for Q2 if its absolute
gate-to-source voltage rating exceeds the maximum voltage
applied to PVCC.
P
LOWER
UPPER
t
Fs is the switching frequency.
= I
= I
SW
O
O
2
2
is the switching interval, and
x r
x r
CC
DS(ON)
DS(ON)
. This option should only be used in
x D +
SW
x (1 - D)
CC
2-160
which increases the upper
D
. The boot capacitor, C
) when the lower MOSFET, Q2
O
1
2
/ V
Io x V
IN
,
IN
x t
CC
SW
. For Q2, a
x Fs
BOOT
CC
HIP6012
FIGURE 10. UPPER GATE DRIVE - DIRECT V
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency will drop one or two
percent as a result. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
HIP6012
HIP6012
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
+
+
-
-
+12V
+12V
VCC
VCC
+
GND
D
GND
VO
BOOT
BOOT
UGATE
PHASE
LGATE
PGND
PVCC
BOOT
UGATE
PHASE
LGATE
PGND
PVCC
-
+5V
+5V
OR +12V
OR +12V
C
BOOT
Q1
Q2
Q1
+5V OR +12V
Q2
+5V OR LESS
D2
CC
D2
NOTE:
V
V
NOTE:
NOTE:
V
NOTE:
V
G-S
G-S
DRIVE OPTION
G-S
G-S
V
V
PVCC
PVCC
CC
CC
- V
- 5V
D