LNBH2 STMicroelectronics, LNBH2 Datasheet - Page 8

• Manufacturer Part Number: LNBH2
• Description: LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE
• Manufacturer: STMicroelectronics

LNBH21
TRANSMITTED DATA (I
When the R/W bit in the chip address is set to 0, the main µP can write on the System Register (SR) of the
LNBH21 via I
left to the diagnostic flags, and are read-only.
X= don't care.
Values are typical unless otherwise specified
RECEIVED DATA (I
The LNBH21 can provide to the Master a copy of the SYSTEM REGISTER information via I2C bus in read
mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the
following master generated clocks bits, the LNBH21 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
- acknowledge the reception, starting in this way the transmission of another byte from the LNBH21;
- no acknowledge, stopping the read mode communication.
While the whole register is read back by the µP, only the two read-only bits OLF and OTF convey
diagnostic informations about the LNBH21.
Values are typical unless otherwise specified.
Values are typical unless otherwise specified
POWER-ON I
The I
the UnderVoltage Lockout threshold (6.7V typ.), the interface will not respond to any I
the System Register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the
V
µP. This is due to 500mV of hysteresis provided in the UVL threshold to avoid false retriggering of the
Power-On reset circuit.
ADDRESS PIN
Connecting this pin to GND the Chip I
4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page 10).
8/20
PCL
PCL
CC
These bits are read exactly the same as
X
they were left after last write operation
0
1
rises above 7.3V typ, the I
2
C interface built in the LNBH21 is automatically reset at power-on. As long as the V
TTX
TTX
X
0
1
2
2
TEN
TEN
C bus. Only 6 bits out of the 8 available can be written by the µP, since the remaining 2 are
C INTERFACE RESET
X
X
0
1
2
LLC VSEL
LLC VSEL
C bus READ MODE)
X
0
0
1
1
2
C BUS WRITE MODE)
X
0
1
0
1
2
C interface becomes operative and the SR can be configured by the main
EN
EN
1
1
1
1
1
1
1
1
1
1
0
2
C interface address is 0001000, but, it is possible to choice among
OTF
OTF
X
X
X
X
X
X
X
X
X
X
X
0
1
OLF
OLF
X
X
X
X
X
X
X
X
X
X
X
0
1
V
V
V
V
22KHz is controlled by DSQIN pin
22KHz tone is ON, DSQIN pin disabled
V
LLC
V
output voltage level controlled by VSEL and LLC
Pulsed (dynamic) current limiting is selected
Static current limiting is selected
Power blocks disabled
T
T
I
I
OUT
OUT
J
J
O
O
O
O
O
O
<140°C, normal operation
>150°C, power block disabled
RX output is ON, output voltage controlled by VSEL and
TX output is ON, 22KHz controlled by DSQIN or TEN,
= 13.25 V, V
= 18V, V
= 19.5 V, V
= 14.25 V, V
<I
>I
OMAX
OMAX
, normal operation
, overload protection triggered
UP
=20 V
UP
UP
UP
= 21.5 V
= 15.25 V
= 16.25 V
Function
Function
2
C command and
CC
stays below