AK5354VT Asahi Kasei Microsystems, AK5354VT Datasheet - Page 10

• Manufacturer Part Number: AK5354VT
• Description: LOW POWER 20 BIT ADC WITH PGA
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
n System Reset & Offset Calibration
The AK5354 should be reset once by bringing PDN pin “L” after power-up. The control register values are initialized by
PDN “L”.
Offset calibration starts by PDN pin “L” to “H”. It takes 4128/fs to offset calibration cycle. During offset calibration, the
ADC digital data outputs of both channels are forced to a 2’s compliment “0”. Output data of settles data equivalent for
analog input signal after offset calibration. IPGA is set MUTE during offset calibration and after offset calibration.
As a normal offset calibration may not be executed, nothing write at address 01H during offset calibration.
When offset calibration is executed once, the calibration memory is held even if each block is powered down (PM0 = “0”
or PM1 = “0”) by power management bits.
MS0054-E-01
ADC Internal
W rite to register
Power Supply
Control register
External clocks
PDN pin
Note: See “Register Definitions” about the condition of each register.
(1). Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(2). If the analog signal does not be input, digital outputs have the offset to op-amp of input and some offset error of a
(3). ADC output is “0” at power down.
(4). This figure shows that MUTE of IPGA is canceled during offset calibration. If MUTE of IPGA is canceled, SDTO
(5). When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK5354 should be in the power down
AIN
SDTO
State
PD:
PM:
CAL:
INIT-1:
Inhibit-1:
Inhibit-2:
(GD). Output signal gradually comes to settle to input signal during a group delay.
internal ADC.
outputs Idle Noise.
(PDN pin = “L” or PM1 bit = “0”) mode.
PDN pin may be “L” at power-up.
Initializing all control registers.
Inhibits writing to all control registers.
Power-down state. ADC is output “0”.
Power-down state by Power Management bit. ADC is output “0”.
During offset calibration cycle. IPGA is set MUTE state.
Enable writing to control registers except address 01H.
Inhibit-1
INIT-2
PD
Figure 8. Power up / Power down Timing Example
(5)
Inhibit-2
GD
4128/fs
CAL
“0”data
The clocks may be stopped.
(4)
- 10 -
Normal
Idle Noise
Normal
GD (1)
(2)
Normal
(3) “0”data
PM
(5)
INIT-1
4128/fs
Normal
(1)
[AK5354]
2001/01
GD