ispPAC10-01PI Lattice Semiconductor, ispPAC10-01PI Datasheet - Page 21

• Manufacturer Part Number: ispPAC10-01PI
• Description: In-System Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor

The EXTEST (external test) instruction is required and
would normally place the device into an external bound-
ary test mode while also enabling the Boundary-Scan
Register to be connected between TDI and TDO. Again,
since the ispPAC10 has no boundary-scan logic, the
device is put in the BYPASS mode to ensure specification
compatibility. The bit code of this instruction is defined by
the 1149.1 standard to be all zeros.
Table 2. ispPAC10 TAP Instructions
The optional IDCODE (identification code) instruction is
incorporated in the ispPAC10 and leaves it in its func-
tional mode when executed. It selects the Device
Identification Register to be connected between TDI and
TDO. The Identification Register is a 32-bit shift register
containing information regarding the IC manufacturer,
device type and version code (see Figure 17). Access to
the Identification Register is immediately available, via a
TAP data scan operation, after power-up of the device,
after a reset using the optional TRST pin, or by issuing a
Test-Logic-Reset instruction. The bit code for this in-
struction is defined by Lattice as shown in Table 2.
The Figure 17. Identification Code (IDCODE)
32-Bit Binary Word for Lattice ispPAC10
IEEE Standard 1149.1 Interface (Continued)
EXTEST
ADDUSR
UBE
VERUSR
PRGUSR
IDCODE
ENCAL
SAMPLE
BYPASS
Instruction
MSB
E 2 Configured
XXXX / 0000 0001 0000 0000 / 0000 0100 001 / 1
Version
(4 bits)
0100h = PAC10
Part Number
(16 bits)
00000
00001
00010
00011
00100
01101
10000
11110
11111
Code
External test. Default to BYPASS.
Address User data register.
User bulk erase.
Verify User data register.
Program User data register.
Read Identification data register.
Enable Calibration sequence.
Sample/Preload. Default to BYPASS.
Bypass (connect TDI to TDO).
Lattice Semiconductor
JEDEC Manfacturer
Identity Code for
Description
(11 bits)
per 1149.1-1990
Constant 1
(1 bit)
LSB
21
ADDUSR (address user register) instruction is a Lattice
defined instruction that selects the user register to be
shifted during a Shift-DR operation. Normal operation of
a device is not interrupted by this instruction. It precedes
a PROGUSR (program user) instruction to shift in a new
configuration and follows a VERUSR (verify user) in-
struction to shift out the current configuration. The bit
code for this instruction is shown in Table 2.
The PRGUSR (program user) is a Lattice instruction that
enables the data shifted into the user register to be
programmed into the non-volatile E
the ispPAC10 and thereby alter its configuration. The
user register is a 109-bit shift register that contains all the
user-controlled parametric and interconnect data per-
taining to the configuration of the ispPAC10. Normal
operation of the device is interrupted during the actual
programming time. A programming operation does not
begin until entry of the Run-Test/Idle state. The time
required to insure data retention is given in the TAP signal
specifications table. The user must ensure that the rec-
ommended programming times are observed. The bit
code for this instruction is shown in Table 2.
VERUSR (verify user) is the next Lattice instruction and
causes the current configuration of the ispPAC10 to be
loaded into the user register. This operation doesn’t
interrupt operation of the device. The current configura-
tion can then be shifted out of the user register immediately
after an ADDUSR instruction is executed. The bit code for
this instruction is shown in Table 2.
ENCAL (enable calibration) is a Lattice instruction that
enables the start of an auto-calibration sequence. This
operation causes all outputs of the device to go to 0V until
the calibration sequence is completed (see timing speci-
fications). As with the programming instructions above,
calibration does not begin until entry of the Run-Test/Idle
state. The completion of the calibration is not dependent,
however, on any further TAP control. This means the
state of the TAP can be returned immediately to the Test-
Logic-Reset state. The only consideration would be to
not clock the TAP during critical analog operations. The
first several milliseconds of the calibration routine are
consumed waiting for configurations to settle, though,
leaving more than enough time to clock the TAP back to
the Test-Logic-Reset state. The bit code for this instruc-
tion is shown in Table 2.
Specifications ispPAC10
2
CMOS memory of