SN54-74LS155 ON Semiconductor, SN54-74LS155 Datasheet - Page 2

• Manufacturer Part Number: SN54-74LS155
• Description: DUAL 1-OF-4 DECODER/ DEMULTIPLEXER
• Manufacturer: ON Semiconductor

FUNCTIONAL DESCRIPTION
plexers with common Address inputs and separate gated
Enable inputs. When enabled, each decoder section accepts
the binary weighted Address inputs (A 0 , A 1 ) and provides four
mutually exclusive active LOW outputs (O 0 – O 3 ). If the Enable
requirements of each decoder are not met, all outputs of that
decoder are HIGH.
enable gate for Decoder “a” requires one active HIGH input
and one active LOW input (E a E a ). In demultiplexing applica-
tions, Decoder “a” can accept either true or complemented
data by using the E a or E a inputs respectively. The enable gate
for Decoder “b” requires two active LOW inputs (E b E b ). The
LS155 or LS156 can be used as a 1-of-8 Decoder/Demulti-
plexer by tying E a to E b and relabeling the common connection
as (A 2 ). The other E b and E a are connected together to form
the common enable.
minterms of two variables. These four minterms are useful in
some applications replacing multiple gate functions as shown
in Fig. a. The LS156 has the further advantage of being able to
LOGIC DIAGRAM
The LS155 and LS156 are Dual 1-of-4 Decoder/Demulti-
Each decoder section has a 2-input enable gate. The
The LS155 and LS156 can be used to generate all four
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
ADDRESS
A 0
H
H
X
X
L
L
A 1
X
X
H
H
L
L
V CC = PIN 16
GND = PIN 8
= PIN NUMBERS
ENABLE “a”
E a
X
H
H
H
H
L
E a
SN54/74LS155 SN54/74LS156
X
H
L
L
L
L
O 0
H
H
H
H
H
L
FAST AND LS TTL DATA
OUTPUT “a”
7
O 1
O 0a
H
H
H
H
H
L
1
E a E a
TRUTH TABLE
6
O 1a
2
O 2
H
H
H
H
H
L
5-2
5
O 2a
13
O 3
H
H
H
H
H
L
AND the minterm functions by tying outputs together. Any
number of terms can be wired-AND as shown below.
f = (E + A 0 + A 1 ) (E + A 0 + A 1 ) (E + A 0 + A 1 )
(E + A 0 + A 1 )
where E = E a + E a ; E = E b + E b
A 0
4
O 3a
ENABLE “b”
A 1
E b
H
X
L
L
L
L
3
9
O 0b
A 0
A 1
A 0
A 1
A 0
A 1
A 0
A 1
E
E
E
E
E b
X
H
L
L
L
L
10
O 1b
O 0
H
H
H
H
H
L
11
O 2b
Figure a
14
E b E b
O 0
O 1
O 2
O 3
OUTPUT “b”
O 1
12
H
H
H
H
H
L
O 3b
15
A 0
A 1
A 0
A 1
A 0
A 1
A 0
A 1
E
E
E
E
O 2
H
H
H
H
H
L
O 3
H
H
H
H
H
L
O 0
O 1
O 2
O 3