ISPGDS14-7J Lattice Semiconductor, ISPGDS14-7J Datasheet - Page 5

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ISPGDS14-7J

Manufacturer Part Number
ISPGDS14-7J
Description
in-system programmable Generic Digital SwitchTM
Manufacturer
Lattice Semiconductor
Datasheet

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Note 1: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Note 2: The default configuration for unused pins is for all configuration bits set to one, which produces a tri-stated output.
I/O Macrocell
I/O Macrocell Configurations
From
Switch
Matrix
From
Switch
Matrix
To
Switch
Matrix
Vcc
Switch
Matrix
Closed only when C0=1 and C1=0
Vcc
C2
0 1
1 0
1 1
0 0
4:1 MUX
5
C1
Configuration for Active High Output
Configuration for Active Low Output
Configuration for Fixed TTL High Output
Configuration for Fixed TTL Low Output
Configuration for Dedicated Input
- C0 = 0.
- C1 = 1.
- C2 = 1.
- C0 = 0.
- C1 = 0.
- C2 = 1.
- C0 = 0.
- C1 = 1.
- C2 = 0.
- C0 = 0.
- C1 = 0.
- C2 = 0.
- C0 = 1.
- C1 = 0.
- C2 = 1.
Specifications ispGDS
C0

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