ISPGDX160-5B272 Lattice Semiconductor, ISPGDX160-5B272 Datasheet - Page 3

• Manufacturer Part Number: ISPGDX160-5B272
• Description: In-System Programmable Generic Digital CrosspointTM
• Manufacturer: Lattice Semiconductor

80 I/O Cells
The ispGDX architecture is different from traditional PLD
architectures, in keeping with its unique application fo-
cus. The block diagram is shown below. The
programmable interconnect consists of a single Global
Routing Pool (GRP). Unlike ispLSI devices, there are no
programmable logic arrays on the device. Control signals
for OEs, Clocks and MUX Controls must come from
designated sets of I/O pins. The polarity of these signals
can be independently programmed in each I/O cell.
Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
The in-system programming process uses either a Bound-
ary Scan based or Lattice ISP protocol. The programming
protocol is selected by the BSCAN/ispEN pin as de-
scribed later.
The various I/O pin sets are also shown in the block
diagram below. The A, B, C, and D I/O pins are grouped
together with one group per side.
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by
two select lines called MUX0 and MUX1 as shown in
Figure 1. ispGDX I/O Cell and GRP Detail (160 I/O Device)
Architecture
I/O 78
I/O 79
I/O 0
I/O 1
•
•
•
•
•
•
Logic "1"
160 Input GRP
Outputs Horizontal
160 I/O Inputs
Programmable
Inputs Vertical
Interconnect
E
• • • • • •
2
CMOS
Clocks
Y0-Y3
Global
Global
Reset
MUXA
MUXB
MUXC
MUXD
4-to-1 MUX
I/O 158
I/O 159
MUX0
I/O 80
I/O 81
MUX1
80 I/O Cells
A
B
Bypass Option
D
CLK
Register
or Latch
3
Reset
• •
•
Specifications ispGDX Family
Figure 1. The four data inputs to the MUX (called MUXA,
MUXB, MUXC and MUXD) come from I/O signals found
in the GRP. Each MUX data input can access one quarter
of the total I/Os. For example, in a 160 I/O ispGDX, each
data input can connect to one of 40 I/O pins. MUX0 and
MUX1 can be driven by designated I/O pins called
MUXsel1 and MUXsel2. Each MUXsel input covers 25%
of the total I/O pins (e.g. 40 out of 160). MUX0 and MUX1
can be driven from either MUXsel1 or MUXsel2. The I/O
cell also includes a programmable flow-through latch or
register that can be placed in the input or output path and
bypassed for combinatorial outputs. As shown in Figure
1, when both register/latch control MUXes select the “A”
path, the register/latch gets its inputs from the 4:1 MUX
and drives the I/O output. When selecting the “B” path,
the register/latch is directly driven by the I/O input while
its output feeds the GRP. The programmable polarity
Clock to the latch or register can be connected to any
I/O in the I/O-Clock set (one-quarter of total I/Os) or to
one of the dedicated clock input pins (Y
dedicated clock inputs gives minimum clock-to-output
delays and minimizes delay variation with fanout. Com-
binatorial output mode may be implemented by a
dedicated architecture bit and bypass MUX. I/O cell
output polarity can be programmed as active high or
active low.
Q
C
R
Programmable
Slew Rate
Boundary
Scan Cell
I/O Cell N
Pull-up
Prog.
I/O Pin
I/O MUX Operation
MUX1 MUX0 DATA INPUT SELECTED
0
0
1
1
0
1
1
0
x
). Use of the
MUXA
MUXB
MUXC
MUXD