L3030 STMicroelectronics, L3030 Datasheet - Page 11

• Manufacturer Part Number: L3030
• Description: SUBSCRIBER LINE INTERFACE KIT
• Manufacturer: STMicroelectronics

Ringing Mode
When ringingis selected(BIT2R= 1,BIT0R = 0), the
control unit L3030 presets the L3000S to operate
between – 48V (– 60V) and + 72V (+ 60V) battery.
Then,settingBIT1 =1, a low levelsignal(0.285Vrms
with frequency range 16-66Hz) applied to pin 41, is
amplified and injected in balancedmode to the line
throughL3000S with a superimposedDC voltageof
24V. The impedance to the line is given by the two
external resistors and the 24V DC polarity can only
be direct.
The firstand the lastringing cycles aresynchronized
by L3030 so that ringing always starts and stops at
zero crossing. Ring trip detection is performed au-
tonomouslyby the SLIC,without anyparticularcom-
mand, using a patented system ; when handset is
lifted, SLIC suspends the ringing signal just remai-
ning inthe ringingmode. Inthiscondition,the control
unit L3030 checks that the loop is closed for a time
equal to two periods of the ringing signal ; if the clo-
sure is confirmed, a flag (BIT0T = 1) is set and the
SLIC waits the new command from the control pro-
cessor. Whereas the loop closure is not confirmed,
the ringing signalis newly appliedto theline, without
setting BIT0T.
DIGITAL INTERFACE
Functional Description
The L3030 states and functions are controlled by
central processor through five wires defining a digi-
tal interface.It is possibleto select the interfacewor-
king mode between SERIAL or PARALLEL (pin 33
tied to a voltage between 4 and 5V).
1) Serial Mode
The five wires of the digital interface have the follo-
wing functions :
- clock (DCLK), entering at pin 21
- data in/data out (DIO), exchanged at pin 20
- input/outputselect (EIA), entering at pin 18
- chip select (NCS), entering at pin 19
- change NCS from in to out (CI), entering at pin 26
The maximum clock frequency is 600Khz.
When EIAsignal is low data are transferredfrom the
card controller into I/O registers of the L3030 selec-
ted by NCS signal tied at low level ; then data are
latched for execution.In this phasea complete 8 bit
word is loaded into internalregister and consequen-
tly NCS signal must remain low for the correspon-
ding 8 clock pulses (DCLK). The EIA signal must
remain at low level at least for the time in whichNCS
signal remain low. The device load data in input re-
gister during the positive edge of clock signal
(DCLK) and store the contents of the register on the
positive edge of NCS signal.
When EIA signal is high data are transferred from
the L3030 selected by NCS tied to low level to the
card controller. The L3030 status is described by
five bits contained in the output register ; the NCS
signalcan remain low for fiveor lessclockpulsesde-
pending if the card controller want to read the com-
plete L3030 status or only a part of it.
Fig. 8, 9 showthe completewrite and read operation
timing. Table 1 shows the meaning of each bit of an
I/O data.
(note 1)
L3000S - L3030
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