K4S161622H-TC55 Samsung semiconductor, K4S161622H-TC55 Datasheet - Page 9

• Manufacturer Part Number: K4S161622H-TC55
• Description: 16Mb H-die SDRAM Specification
• Manufacturer: Samsung semiconductor

SDRAM 16Mb H-die(x16)
AC OPERATING TEST CONDITIONS
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
Col. address to col. address delay
Mode Register Set cycle time
Number of valid out-
put data
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Output
(Fig. 1) DC Output Load Circuit
870Ω
Parameter
Parameter
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
3.3V
1200Ω
30pF
t
t
t
t
t
t
Symbol
t
t
t
RAS(max)
t
RRD(min)
RCD(min)
t
CCD(min)
MRS(min)
RAS(min)
RDL(min)
CDL(min)
BDL(min)
RC
RP(min)
V
V
t
CC
OH
OL
(
min
(DC) = 0.4V, I
(V
(DC) = 2.4V, I
)
DD
= 3.3V±0.3V, T
16.5
16.5
38.5
Min
5.5
10
55
11
-
55
2
OL
1000
OH
Max
100
-
-
-
-
-
= 2mA
= -2mA
A
= 0 to 70°C)
Min
10
12
18
18
42
60
6
-
tr / tf = 1 / 1
See Fig. 2
2.4 / 0.4
60
Value
1.4
1.4
1000
Max
Output
100
-
-
-
-
-
1
1
1
2
2
1
Min
10
14
20
20
49
69
7
-
(Fig. 2) AC Output Load Circuit
70
1
1000
Max
100
-
-
-
-
-
Rev. 1.5 August 2004
Z0=50Ω
Min
CMOS SDRAM
10
16
20
20
48
70
8
-
80
1000
Max
100
-
-
-
-
-
Vtt=1.4V
Unit
50Ω
30pF
ns
V
V
V
Unit
CLK
CLK
CLK
CLK
CLK
ns
ns
ns
ns
ns
us
ns
ea
Note
2,8
1
2
2
4