SAA4978 Philips, SAA4978 Datasheet - Page 5

• Manufacturer Part Number: SAA4978
• Description: Picture Improved Combined Network PICNIC
• Manufacturer: Philips

Philips Semiconductors
FUNCTIONAL DESCRIPTION
Applicable video standards
The integrated 16 : 9 compressor can be used for the
following video standards; B, C, D, G, H, I, K, K1, L,
M and N. standards D, I, K, K1 and L will show a reduced
video bandwidth above 5 MHz.
Clamping circuit
The clamping circuits clamp the video input signals Y,
(B Y) and (R Y) to the DC level of the clamp reference
signal fed from the clamp reference circuit. This is
necessary to ensure that the input signals are in the
correct input voltage range for the 5 MHz low-pass filters
and the SC line memories.
Internal pre filters
Before the signals are sampled in the time discrete and
amplitude continuous area, low-pass filtering is necessary
to avoid any aliasing. Even if the inputs have already been
low-pass filtered further filtering is advantageous for the
electromagnetic compatibility (EMC). The same transfer
function is used for all three low-pass filters because of the
same bandwidth for the luminance and chrominance
signals (up to 5 MHz).
SC line memories
After the low-pass filters the input signals are fed to the SC
line memories. The signals are sampled at a clock
frequency of 13.5 MHz. One video line later the signals are
read with a clock frequency of 18 MHz in the compression
mode. The result of the different clock frequencies is a
horizontal compression by a factor of
the horizontal starting pulses for the SC line memories are
fed from the controller.
Two line memories are required for each signal path
because in the compression mode, in one video line the
signals are sampled to the SC line memories with
13.5 MHz and one video line later the signals are read with
18 MHz. In the bypass mode, via the SC line memories, in
one video line the signals are sampled with 13.5 MHz and
one video line later the signals are read with 13.5 MHz.
The SC line memories are suitable for signals with a
bandwidth up to 5 MHz. With a multiplexer (MUX) behind
the SC line memories, the sampled video signal is
connected to the internal post filters.
1995 Oct 05
Monolithic integrated 16 : 9 compressor
4
3
. The clocks and
5
Output multiplexer MUX Y, MUX (B Y) and MUX (R Y)
The output multiplexers are controlled via C1 and C2 fed
from the controller. The multiplexers are used to connect
one of the four input signals to the output and, also, enable
fast switching.
The input signals of the multiplexers for one component
[Y, (B Y) or (R Y)] are as follows:
The horizontal separation circuit
The 54 MHz horizontal PLL is locked to the positive edge
of the digital HREF signal, which is generated in the
horizontal separation circuit. It is also possible to use the
positive edge of the burst key of a sandcastle signal.
54 MHz horizontal PLL
The 13.5 MHz clock frequency for the sampling clock and
the 18 MHz clock frequency for the reading clock are
generated in the 54 MHz horizontal PLL. The 13.5 MHz
clock and the 18 MHz clock are line locked.
Clamp reference
Reference voltages are generated In the clamp reference
block. These DC signals are used in the clamping circuits
as input signals for the output multiplexers and as
reference voltages for the SC line memories.
Four external capacitors at the pins C
and BGREF respectively are necessary to provide
smoothing for the reference voltages. A black level
reference signal is available at CLAOUT.
The output signal of the post filter
The uncompressed signal after the input clamping
The clamping reference signal
The signal for the side panel determined by YSIDE,
BYSIDE and RYSIDE.
Preliminary specification
LMY
SAA4981
, C
LMBY
, C
LMRY