GAL6001B-30LJ Lattice Semiconductor, GAL6001B-30LJ Datasheet - Page 9

• Manufacturer Part Number: GAL6001B-30LJ
• Description: High Performance E2CMOS FPLA Generic Array Logic
• Manufacturer: Lattice Semiconductor

1) Refer to Switching Test Conditions section.
PARAMETER
AC Switching Characteristics
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
max
wh1
wh2
t
arr1
arr2
pd1
pd2
pd3
co1
co2
co3
co4
su1
su2
su3
su4
su5
su6
arw
wl1
wl2
dis
h1
h2
h3
h4
en
ar
COND
TEST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C
A
A
A
A
A
A
A
B
A
1
.
Combinatorial Input to Combinatorial Output
Feedback or I/O to Combinatorial Output
Transparent Latch Input to Combinatorial Output
Input Latch ICLK to Combinatorial Output Delay
Input Reg. ICLK to Combinatorial Output Delay
Output D/E Reg. OCLK to Output Delay
Output D Reg. Sum Term CLK to Output Delay
Setup Time, Input before Input Latch ICLK
Setup Time, Input before Input Reg. ICLK
Setup Time, Input or Feedback before D/E Reg. OCLK
Setup Time, Input or Feedback before D Reg. Sum Term CLK
Setup Time, Input Reg. ICLK before D/E Reg. OCLK
Setup Time, Input Reg. ICLK before D Reg. Sum Term CLK
Hold Time, Input after Input Latch ICLK
Hold Time, Input after Input Reg. ICLK
Hold Time, Input or Feedback after D/E Reg. OCLK
Hold Time, Input or Feedback after D Reg. Sum Term CLK
Maximum Clock Frequency, OCLK
ICLK or OCLK Pulse Duration, High
Sum Term CLK Pulse Duration, High
ICLK or OCLK Pulse Duration, Low
Sum Term CLK Pulse Duration, Low
Reset Pulse Duration
Input or I/O to Output Enabled
Input or I/O to Output Disabled
Input or I/O to Asynchronous Reg. Reset
Asynchronous Reset to OCLK Recovery Time
Asynchronous Reset to Sum Term CLK Recovery Time
DESCRIPTION
Over Recommended Operating Conditions
9
Specifications GAL6001
MIN. MAX.
2.5
2.5
7.5
25
30
15
10
27
10
15
10
15
15
20
10
—
—
—
—
—
—
—
—
—
—
5
5
0
COM
-30
30
30
35
35
35
12
35
25
25
35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns