AM29BDS643D AMD [Advanced Micro Devices], AM29BDS643D Datasheet

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... PRELIMINARY Am29BDS643D 64 Megabit ( 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory DISTINCTIVE CHARACTERISTICS Single 1.8 volt read, program and erase (1.7 to 1.9 volt) Multiplexed Data and Address for reduced I/O count — A0–A15 multiplexed as D0–D15 — Addresses are latched with AVD# control inputs ...

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... The system can also place the device into the standby mode. Power consumption is greatly re- duced in both modes. Am29BDS643D , WP# locks the two outermost sec all sectors are locked. PP ...

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... Device) ............................................................ 41 Figure 21. Back-to-Back Read/Write Cycle Timings ...................... 42 Erase and Programming Performance . . . . . . . 43 Data Retention Physical Dimensions FDE048—48-Pin Fine-Pitch Ball Grid Array (FBGA package ............................................................. 44 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46 Revision A (June 20, 2000) .................................................... 46 Revision A+1 (November 27, 2000) ....................................... 46 Revision A+2 (November 30, 2000) ....................................... 46 Revision A+3 (December 21, 2000) ....................................... 46 Am29BDS643D 3 ...

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... OE RDY Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Logic Y-Decoder Timer X-Decoder Burst Address Counter A0–A21 Am29BDS643D Asynchronous Speed Option Max Access Time ACC Max CE# Access Max OE# Access – A/DQ0 A/DQ15 PS Buffer Input/Output ...

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... A0–A21 A0–A21 STATE RESET# CONTROL & WE# COMMAND CE# REGISTER AVD# DQ0–DQ15 A0–A21 Note: A0–A15 are multiplexed with DQ0–DQ15 Upper Bank Address Upper Bank X-Decoder Status Control X-Decoder Lower Bank Lower Bank Address Am29BDS643D OE# DQ0–DQ15 5 ...

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... Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods compromised if the package body is exposed to temperatures above 150 C for prolonged periods of time. Am29BDS643D A8 A9 A10 A19 A17 ...

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... SA133 and SA134 accelerates programming; PP automatically places device in unlock bypass mode program and erase functions. Should LOGIC SYMBOL 6 A16–A21 CLK CE# OE# WE# RESET# AVD# Am29BDS643D , disables IL for all other conditions A/DQ0– A/DQ15 PS RDY 7 ...

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... Fine-Pitch Grid Array (FBGA) 0.50 mm pitch package (FDE048) CLOCK RATE MHz MHz SPEED See Product Selector Guide and Valid Combination BOOT CODE SECTOR ARCHITECTURE T = Top sector Order Number Am29BDS643DT9AWLI Am29BDS643DT9BWLI Am29BDS643D Valid Combinations Package Marking N643DTH9AVI N643DTH9BVI ...

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... Enable PS Mode command sequence at this time, but ) is the delay from note that the PS mode can only be disabled by a hard- ware reset. (See “Command Definitions” for further details). The initial word is output t the first CLK cycle. Subsequent words are output t Am29BDS643D CLK AVD# I I/O ...

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... To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive CLK, AVD# and CE OE when providing an address to the device, IH Am29BDS643D ; if the word on the data bus for IH for non-inverted data. ...

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... Output Disable Mode ± 0 When the OE# input for impedance state. Am29BDS643D ±0.2 V, the device RESET# is CC4 but not within V ±0.2 V, the standby cur- SS ...

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... WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one CE# and WE# must be a logical zero while OE logical one. Am29BDS643D , the device does not ac- LKO CC is greater than CC . LKO . To initiate a write cycle, IH ...

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... Kwords SA25 32 Kwords SA26 32 Kwords SA27 32 Kwords SA28 32 Kwords SA29 32 Kwords SA30 32 Kwords Am29BDS643D (x16) Address Range 000000h—007FFFh 008000h—00FFFFh 010000h—017FFFh 018000h—01FFFFh 020000h—027FFFh 028000h—02FFFFh 030000h—037FFFh 038000h—03FFFFh 040000h—047FFFh 048000h—04FFFFh 050000h—057FFFh 058000h—05FFFFh 060000h— ...

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... Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Am29BDS643D (x16) Address Range 0F8000h—0FFFFFh 100000h—107FFFh 108000h—10FFFFh 110000h—117FFFh 118000h—11FFFFh 120000h—127FFFh 128000h—12FFFFh 130000h—137FFFh 138000h—13FFFFh 140000h—147FFFh 148000h—14FFFFh 150000h—157FFFh 158000h— ...

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... SA109 32K words SA110 32K words SA111 32K words SA112 32K words SA113 32K words Am29BDS643D (x16) Address Range 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h– ...

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... Am29BDS643D (x16) Address Range 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h– ...

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... F0h (reset command). Note that the last two outermost boot sectors can be locked by taking the WP# signal all sectors are locked; if the V IL sectors are unlocked. Am29BDS643D Total Initial Access A12 Cycles Data ...

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... Only erase operations can convert a “0” “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to prima- rily program to a bank faster than using the standard Am29BDS643D Address Read Data (BA) + 00h 0001h (BA) + 01h ...

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... The system can determine the sta- tus of the erase operation by using DQ7 or DQ6/DQ2. Refer to the Write Operation Status section for infor- mation on these status bits. Am29BDS643D START Write Program Command Sequence Data Poll ...

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... Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. Am29BDS643D ...

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... Write Erase Command Sequence from System No Data = FFh? Erasure Completed Notes: 1. See Table 4 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 2. Erase Operation Am29BDS643D START Data Poll Embedded Erase algorithm in progress Yes 21 ...

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... The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 15. The addresses in the third cycle must contain, on A12 and A13, the additional wait counts to be set. See “Set Wait State Command Sequence”. Am29BDS643D Fourth Fifth Sixth Addr ...

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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 3. Data# Polling Algorithm Am29BDS643D Yes No Yes Yes No ...

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... FAIL Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 4. Toggle Bit Algorithm Am29BDS643D No Yes Yes No Yes ...

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... The device may output a “1” on DQ5 if the system tries to program a “1” location that was previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device Am29BDS643D and DQ2 does not toggle. also toggles. ...

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... Table 6 shows the status of DQ3 relative to the other status bits. Table 6. Write Operation Status DQ7 (Note 2) DQ6 DQ7# Toggle 0 Toggle 1 No toggle Data Data DQ7# Toggle Am29BDS643D DQ5 DQ2 (Note 1) DQ3 (Note 2) 0 N/A No toggle 0 1 Toggle 0 N/A Toggle Data Data ...

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... Operating ranges define those limits between which the func- tionality of the device is guaranteed +0.8 V –0 0 –2.0 V Figure 5. Maximum Negative +2 –2.0 V for SS +0.5 V 1.0 V Figure 6. Maximum Positive Am29BDS643D Overshoot Waveform Overshoot Waveform 27 ...

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... CC CC min I = –100 µ min = V max reasserted, the last data prior to OE ns. Typical sleep mode current is equal to I ACC and V currents Am29BDS643D Min Typ Max Unit ±1 µA ±1 µ 0 3 ...

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... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am29BDS643D 9A, 9B Unit 0.0– ...

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... Max Min Min Min Min Min Max Max Max Max Min Min Min Max 1 cycle wait state when PS enabled 25 ns typ. t BACC Da Figure 9. Burst Mode Read (54 MHz) Am29BDS643D 9A 9B (40 MHz) (54 MHz) Unit 120 106 ...

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... If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY cycle wait state when PS enabled 25 ns typ. t BACC Da Figure 10. Burst Mode Read (40 MHz) Am29BDS643D t CEZ t RACC t BDH ...

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... Note Read Address Read Data Read Toggle and Data# Polling OEH ACC RA t AAVDH t AAVDS t AVDP Figure 11. Asynchronous Mode Read Am29BDS643D 9A, 9B Max 90 Max 90 Min 12 Min 5 Min 7 Max 20 Min 0 Min 10 Max 10 t OEZ Valid RD ...

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... Reset Timings NOT during Embedded Algorithms CE#, OE# RESET Description Max Max Min Min Min Ready Reset Timings during Embedded Algorithms t Ready t RP Figure 12. Reset Timings Am29BDS643D All Speed Options Unit 20 s 500 ns 500 ns 200 ...

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... Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 3. Does not include the preprogramming time Rise and Fall Time Setup Time (During Accelerated Programming) Setup Time Am29BDS643D 9A, 9B Unit Min 80 ns Min 5 ...

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... A16–A21 are don’t care during command sequence unlock cycles WPH valid only when PS mode is enabled Figure 13. Program Operation Timings Am29BDS643D Read Status Data Complete Progress t WHWH1 35 ...

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... Address bits A16–A21 are don’t cares during unlock cycles in the command sequence. Figure 14. Chip/Sector Erase Operations 555h for 10h for chip erase chip erase SA 30h WPH t WC Am29BDS643D Read Status Data Complete Progress t WHWH2 ...

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... PP 2. Use setup and hold times from conventional program operation. 3. Sectors must be unlocked using the Sector Lock/Unlock command sequence prior to raising V Figure 15. Accelerated Unlock Bypass Programming Timing A0h t VPS VPP Am29BDS643D Don't Care ...

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... VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. Figure 17. Toggle Bit Timings (During Embedded Algorithm CEZ t OEZ VA Status Data VA VA Status Data VA Am29BDS643D Status Data t CEZ t OEZ Status Data ...

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... enabled, RDY will be low for an additional cycle prior to the boundary crossing latency. Figure 18. Latency with Boundary Crossing C62 C63 C63 C63 latency D62 D63 Am29BDS643D C64 C65 C66 C67 RACC D64 D65 D66 ...

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... Note: Devices should be programmed with wait states as discussed in the “Programmable Wait State” section on page 10. Figure 19. Initial Access with Power Saving (PS) Function and Address Boundary Latency function is set to 02h; 6 cycles total) High Am29BDS643D 1 additional 2 additional PS high if data is inverted, wait state to wait states if low if data is not inverted indicate PS ...

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... Figure 20. Example of Five Wait States Insertion (Non-Handshaking Device total number of clock cycles following AVD# falling edge number of clock cycles programmed Am29BDS643D D0 D1 Rising edge of next clock cycle following last wait state triggers next burst data ...

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... Read status (at least two cycles) in same bank and/or array data from other bank OEH ACC SR Am29BDS643D Begin another write or program command sequence GHWL RD 555h AAh ...

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... Max (Note 2) 1.5 15 0.3 5 194 11.5 360 4 210 48 144 1.8 V, 100,000 cycles. CC Test Conditions 150 C 125 C Am29BDS643D Unit Comments s Excludes 00h programming prior to erasure (Note 4) s Excludes system level µs overhead (Note 5) µs Excludes system level s overhead (Note million cycles. Additionally, CC Min Unit ...

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... PHYSICAL DIMENSIONS* FDE048—48-Pin Fine-Pitch Ball Grid Array (FBGA package * For reference only. BSC is an ANSI standard for Basic Space Centering Am29BDS643D ...

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... PHYSICAL DIMENSIONS FDE048—48-Pin Fine-Pitch Ball Grid Array (FBGA (continued Am29BDS643D 45 ...

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... Figure 11, Asynchronous Mode Read Corrected endpoint for t Figure 17, Toggle Bit Timings (During Embedded Algorithm) Corrected OE# waveform during second VA (valid address) period. Revision A+3 (December 21, 2000) Figure 9, Burst Mode Read (54 MHz) and Figure 10, Burst Mode Read (40 MHz) Corrected RDY waveform. Am29BDS643D specification. AAVDS ...