MT48LC4M32B2F5-7IT:G Micron Semiconductor Products, MT48LC4M32B2F5-7IT:G Datasheet - Page 4

• Manufacturer Part Number: MT48LC4M32B2F5-7IT:G
• Manufacturer: Micron Semiconductor Products

Specifications of MT48LC4M32B2F5-7IT:G

• Date_code: 10+

128Mb: x32 SDRAM
Features
List of Figures
Figure 1: 4 Meg x 32 Functional Block Diagram ................................................................................................. 8
Figure 2: 86-Pin TSOP Pin Assignments (Top View) ........................................................................................... 9
Figure 3: 90-Ball FBGA Ball Assignments (Top View) ....................................................................................... 10
Figure 4: 86-Pin Plastic TSOP II (400 mil) – Revision L ..................................................................................... 12
Figure 5: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P ...................................................................... 13
Figure 6: 90-Ball VFBGA (8mm x 13mm) ......................................................................................................... 14
Figure 7: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 16
Figure 8: Example: Temperature Test Point Location, 90-Ball VFBGA (Top View) .............................................. 17
Figure 9: ACTIVE Command .......................................................................................................................... 23
Figure 10: READ Command ........................................................................................................................... 24
Figure 11: WRITE Command ......................................................................................................................... 25
Figure 12: PRECHARGE Command ................................................................................................................ 26
Figure 13: Initialize and Load Mode Register .................................................................................................. 34
Figure 14: Mode Register Definition ............................................................................................................... 36
Figure 15: CAS Latency .................................................................................................................................. 39
t
t
t
Figure 16: Example: Meeting
RCD (MIN) When 2 <
RCD (MIN)/
CK < 3 .......................................................... 40
Figure 17: Consecutive READ Bursts .............................................................................................................. 42
Figure 18: Random READ Accesses ................................................................................................................ 43
Figure 19: READ-to-WRITE ............................................................................................................................ 44
Figure 20: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 45
Figure 21: READ-to-PRECHARGE .................................................................................................................. 45
Figure 22: Terminating a READ Burst ............................................................................................................. 46
Figure 23: Alternating Bank Read Accesses ..................................................................................................... 47
Figure 24: READ Continuous Page Burst ......................................................................................................... 48
Figure 25: READ – DQM Operation ................................................................................................................ 49
Figure 26: WRITE Burst ................................................................................................................................. 50
Figure 27: WRITE-to-WRITE .......................................................................................................................... 51
Figure 28: Random WRITE Cycles .................................................................................................................. 52
Figure 29: WRITE-to-READ ............................................................................................................................ 52
Figure 30: WRITE-to-PRECHARGE ................................................................................................................. 53
Figure 31: Terminating a WRITE Burst ............................................................................................................ 54
Figure 32: Alternating Bank Write Accesses ..................................................................................................... 55
Figure 33: WRITE – Continuous Page Burst ..................................................................................................... 56
Figure 34: WRITE – DQM Operation ............................................................................................................... 57
Figure 35: READ With Auto Precharge Interrupted by a READ ......................................................................... 59
Figure 36: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 60
Figure 37: READ With Auto Precharge ............................................................................................................ 61
Figure 38: READ Without Auto Precharge ....................................................................................................... 62
Figure 39: Single READ With Auto Precharge .................................................................................................. 63
Figure 40: Single READ Without Auto Precharge ............................................................................................. 64
Figure 41: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 65
Figure 42: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 65
Figure 43: WRITE With Auto Precharge ........................................................................................................... 66
Figure 44: WRITE Without Auto Precharge ..................................................................................................... 67
Figure 45: Single WRITE With Auto Precharge ................................................................................................. 68
Figure 46: Single WRITE Without Auto Precharge ............................................................................................ 69
Figure 47: Auto Refresh Mode ........................................................................................................................ 71
Figure 48: Self Refresh Mode .......................................................................................................................... 73
Figure 49: Power-Down Mode ........................................................................................................................ 74
Figure 50: Clock Suspend During WRITE Burst ............................................................................................... 75
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128mb_x32_sdram.pdf - Rev. Q 1/12 EN
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