ISPLSI2064E200LT100 Lattice Semiconductor Corp., ISPLSI2064E200LT100 Datasheet

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ISPLSI2064E200LT100

Manufacturer Part Number
ISPLSI2064E200LT100
Description
QFP100
Manufacturer
Lattice Semiconductor Corp.
Datasheet

Specifications of ISPLSI2064E200LT100

Date_code
04+
• SuperFAST HIGH DENSITY IN-SYSTEM
• HIGH PERFORMANCE E
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
• OFFERS THE EASE OF USE AND FAST SYSTEM
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2064e_06
Features
PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 I/O Pins, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— 100% Functionally and JEDEC Upward Compatible
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG™ In-System Programmable via IEEE 1149.1
— User-Selectable 3.3V or 5V I/O Supports Mixed
— PCI Compatible Outputs
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Machines, Address Decoders, etc.
with ispLSI 2064 Devices
f
t
(JTAG) Test Access Port
Voltage Systems
Market and Improved Product Quality
Logic and Structured Designs
Minimize Switching Noise
Interconnectivity
max = 200 MHz Maximum Operating Frequency
pd = 4.5 ns Propagation Delay
2
CMOS
®
TECHNOLOGY
1
The ispLSI 2064E is a High Density Programmable Logic
Device. The device contains 64 Registers, 64 Universal
I/O pins, four Dedicated Input Pins, three Dedicated
Clock Input Pins, two dedicated Global OE input pins and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2064E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2064E offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.
The basic unit of logic on the ispLSI 2064E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Functional Block Diagram
Description
A0
A2
A3
A1
A4
GLB
SuperFAST™ High Density PLD
Output Routing Pool (ORP)
ispLSI
B7
B7
A5
Global Routing Pool
Logic
Array
Output Routing Pool (ORP)
Input Bus
In-System Programmable
(GRP)
D Q
D Q
D Q
D Q
B6
B6
Input Bus
A6
B5
B5
A7
®
2064E
B4
B4
January 2002
B3
B0
B2
B1
0139/2064E

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