ISPLSI2096E100LT128 Lattice Semiconductor Corp., ISPLSI2096E100LT128 Datasheet

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ISPLSI2096E100LT128

Manufacturer Part Number
ISPLSI2096E100LT128
Description
TQFP100
Manufacturer
Lattice Semiconductor Corp.
Datasheet
• SUPERFAST HIGH DENSITY IN-SYSTEM
• HIGH PERFORMANCE E
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
• OFFERS THE EASE OF USE AND FAST SYSTEM
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2096e_04
Features
PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— 100% Functional/JEDEC Upward Compatible with
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG™ In-System Programmable via IEEE 1149.1
— User-Selectable 3.3V or 5V I/O Supports Mixed-
— PCI Compatible Outputs
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Machines, Address Decoders, etc.
ispLSI 2096 Devices
f
t
(JTAG) Test Access Port
Voltage Systems
Market and Improved Product Quality
Logic and Structured Designs
Minimize Switching Noise
Interconnectivity
max = 180 MHz Maximum Operating Frequency
pd = 5.0 ns Propagation Delay
2
CMOS
®
TECHNOLOGY
1
The ispLSI 2096E is a High Density Programmable Logic
Device. The device contains 96 Registers, 96 Universal
I/O pins, six Dedicated Input pins, three Dedicated Clock
Input pins, two dedicated Global OE input pins and a
Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 2096E features 5V in-system programmability
and in-system diagnostic capabilities. The ispLSI 2096E
offers non-volatile reprogrammability of all logic, as well
as the interconnect to provide truly reconfigurable sys-
tems.
The basic unit of logic on the ispLSI 2096E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or
registered.Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bi-
directional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be pro-
grammed independently for fast or slow output slew rate
to minimize overall output switching noise. By connecting
Functional Block Diagram
Description
Output Routing Pool (ORP)
Output Routing Pool (ORP)
GLB
SuperFAST™ High Density PLD
Logic
Array
ispLSI
D Q
D Q
D Q
D Q
In-System Programmable
Global Routing Pool
Output Routing Pool (ORP)
Output Routing Pool (ORP)
(GRP)
®
2096E
January 2002
0919/2096E

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