ISPLSI319270LQI Lattice Semiconductor Corp., ISPLSI319270LQI Datasheet

ISPLSI319270LQI

Manufacturer Part Number

ISPLSI319270LQI

Description

QFP240

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPLSI319270LQI.pdf (15 pages)

Specifications of ISPLSI319270LQI

Date_code

08+

Current page: 1 of 15
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• HIGH-DENSITY PROGRAMMABLE LOGIC

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

3192_08

Features

— 192 I/O Pins

— 9000 PLD Gates

— 384 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

— Supports ISP™ or ispJTAG™ Programming

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Debugging

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

— PC and UNIX Platforms

Market, and Improved Product Quality

Machines, Address Decoders, etc.

Logic and Structured Designs

mize Switching Noise

Interconnectivity

Tools, Timing Simulator and ispANALYZER™

max = 100 MHz Maximum Operating Frequency

pd = 10 ns Propagation Delay

CMOS

TECHNOLOGY

The ispLSI 3192 is a High Density Programmable Logic

Device containing 384 Registers, 192 Universal I/O pins,

five Dedicated Clock Input Pins, twelve Output Routing

Pools (ORP), and a Global Routing Pool (GRP) which

allows complete inter-connectivity between all of these

elements. The ispLSI 3192 features 5-Volt in-system

programmability and in-system diagnostic capabilities.

The ispLSI 3192 offers non-volatile reprogrammability of

the logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 3192 device is the

Twin Generic Logic Block (Twin GLB) labelled A0, A1...F3.

There are a total of 24 of these Twin GLBs in the ispLSI

3192 device. Each Twin GLB has 24 inputs, a program-

mable AND array and two OR/Exclusive-OR Arrays, and

eight outputs which can be configured to be either com-

binatorial or registered. All Twin GLB inputs come from

the GRP.

Functional Block Diagram

Description

High Density Programmable Logic

ORP

Global Routing Pool

ispLSI

Array

D Q

ORP

Twin

GLB

ORP

3192

June 2002

Boundary

0139/3192

Scan

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