MBM29LV800BA70PFTN Fujitsu, MBM29LV800BA70PFTN Datasheet

MBM29LV800BA70PFTN

Manufacturer Part Number

MBM29LV800BA70PFTN

Description

TSSOP-48

Manufacturer

Fujitsu

Datasheets

1.MBM29LV800BA70PFTN.pdf (55 pages)

2.MBM29LV800BA70PFTN.pdf (56 pages)

Specifications of MBM29LV800BA70PFTN

Date_code

04+

Current page: 1 of 55
Download datasheet (340Kb)

FUJITSU SEMICONDUCTOR

FLASH MEMORY

CMOS

8M (1M

MBM29LV800TA

Ordering Part No.

Max Address Access Time (ns)

Max CE Access Time (ns)

Max OE Access Time (ns)

DESCRIPTION

The MBM29LV800TA/BA are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K

words of 16 bits each. The MBM29LV800TA/BA are offered in a 48-pin TSOP(1), 44-pin SOP , and 48-ball FBGA

packages. These devices are designed to be programmed in-system with the standard system 3.0 V V

12.0 V V

in standard EPROM programmers.

The standard MBM29LV800TA/BA offer access times 70 ns and 90 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),

write enable (WE), and output enable (OE) controls.

The MBM29LV800TA/BA are pin and command set compatible with JEDEC standard E

written to the command register using standard microprocessor write timings. Register contents serve as input

to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch

addresses and data needed for the programming and erase operations. Reading data out of the devices is similar

to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV800TA/BA are programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the devices automatically time the erase pulse widths and

verify proper cell margin.

PRODUCT LINE UP

DATA SHEET

and 5.0 V V

Part No.

are not required for write or erase operations. The devices can also be reprogrammed

= 3.3 V

= 3.0 V

8/512K

-70/-90

+0.3 V

–0.3 V

+0.6 V

–0.3 V

/MBM29LV800BA

MBM29LV800TA/MBM29LV800BA

-70

—

16) BIT

PROMs. Commands are

-70/-90

DS05-20845-6E

-90

—

(Continued)

supply.

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