MBM29PL160TD75PFTN Fujitsu, MBM29PL160TD75PFTN Datasheet
MBM29PL160TD75PFTN
Manufacturer Part Number
MBM29PL160TD75PFTN
Description
TSOP
Manufacturer
Fujitsu
Specifications of MBM29PL160TD75PFTN
Date_code
02+
FUJITSU SEMICONDUCTOR
PAGE MODE FLASH MEMORY
CMOS
16M (2M
MBM29PL160TD
Embedded Erase
FEATURES
• Single 3.0 V read, program and erase
• Compatible with JEDEC-standard commands
• Compatible with MASK ROM pinouts
• Minimum 100,000 program/erase cycles
• High performance
• An 8 words page read mode function
• Sector erase architecture
• Boot Code Sector Architecture
• Embedded Erase
• Embedded program
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
• Automatic sleep mode
• Low V
DATA SHEET
Minimizes system level power requirements
Uses same software commands as E
48-pin TSOP (I) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type)
44-pin SOP (Package suffix: PF)
25 ns maximum page access time (75ns maximum random access time)
One 8K word, two 4K words, one 112K word, and seven 128K words sectors in word mode
One 16K byte, two 8K bytes, one 224K byte, and seven 256K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
T = Top sector
B = Bottom sector
Automatically pre-programs and erases the chip or any sector
Automatically programs and verifies data at specified address
Hardware method for detection of program or erase cycle completion
When addresses remain stable, automatically switches themselves to low power mode
CC
TM
write inhibit
and Embedded Program
TM
Algorithms
TM
Algorithms
2.5 V
TM
are trademarks of Advanced Micro Devices, Inc.
-75/-90
8/1M
2
PROMs
/MBM29PL160BD
16) BIT
DS05-20872-1E
-75/-90
(Continued)
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