ZL30130GGG2 Zarlink Semiconductor, ZL30130GGG2 Datasheet

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ZL30130GGG2

Manufacturer Part Number

ZL30130GGG2

Description

Manufacturer

Zarlink Semiconductor

Datasheet

1.ZL30130.pdf (12 pages)

Specifications of ZL30130GGG2

Lead_time

2 weeks

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Bonase Electronics (HK) Co., Limited

Part Number:

ZL30130GGG2

Manufacturer:

ZARLINK

Quantity:

2 266

Current page: 1 of 12
Download datasheet (214Kb)

Features

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Supports the requirements of ITU-T G.8262 for

synchronous Ethernet Equipment slave Clocks

(EEC option 1 and 2)

Supports the requirements of Telcordia GR-1244

Stratum 2/3/3E and GR-253, ITU-T G.812, G.813,

and G.781 SETS

Meets the SONET/SDH jitter generation

requirements up to OC-12/STM-4

Synchronizes to telecom reference clocks (2 kHz,

N*8 kHz up to 77.76 MHz, 155.52 MHz) or to

Ethernet reference clocks (25 MHz, 50 MHz,

62.5 MHz, 125 MHz)

Supports composite clock inputs (64 kHz, 64 kHz +

8 kHz, 64kHz + 8 kHz + 400 Hz)

Generates standard SONET/SDH clock rates (e.g.

19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,

622.08 MHz) or Ethernet clock rates (e.g. 25 MHz,

50 MHz, 125 MHz) for synchronizing Gigabit

Ethernet PHYs

Programmable output synthesizers (P0, P1)

generate telecom clock frequencies from any

multiple of 8 kHz up to 100 MHz

Generates several styles of telecom frame pulses

with selectable pulse width, polarity and frequency

Provides two DPLLs which are independently

configurable through a serial interface

sync0

sync1

sync2

sync8

ref0

ref1

ref2

ref3

ref4

ref5

ref6

ref7

ref8

/N1

/N2

osci

Ref/Sync

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Monitors

Input

Ports

m ode

osco

Copyright 2008, Zarlink Semiconductor Inc. All Rights Reserved.

lock

hold

ref

ref

Figure 1 - Functional Block Diagram

dpll2_ref

m

n

/sync

n

Zarlink Semiconductor Inc.

Stratum 2/3/3E System Synchronizer/SETS

I

2

C/SPI

DPLL2

DPLL1

T4

T0

1

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Applications

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JTAG

Internal state machine automatically controls

mode of operation (free-run, locked, holdover)

Flexible input reference monitoring automatically

disqualifies references based on frequency and

phase irregularities

Provides automatic reference switching and

holdover during loss of reference input

Supports master/slave configuration and dynamic

input to output delay compensation for

AdvancedTCA

Configurable input to output delay and output to

output phase alignment

ITU-T G.8262 System Timing Cards which support

1GbE interfaces

Telcordia GR-253 Carrier Grade SONET/SDH

Stratum 2/3E/3 System Timing Cards

System Timing Cards which supports ITU-T G.781

SETS (SDH Equipment Timing Source)

ZL30130GGG

ZL30130GGG2

OC-12/STM-4 SONET/SDH/GbE

*Pb Free Tin/Silver/Copper

Ordering Information

TM

-40

SONET/SDH/

Synthesizer

Synthesizer

Synthesizer

Feedback

Ethernet

100 Pin CABGA

100 Pin CABGA*

o

APLL

P1

C to +85

P0

Short Form Data Sheet

o

C

ZL30130

p0_clk0

p0_clk1

p0_fp0

p0_fp1

p1_clk0

p1_clk1

ext_fb_clk

diff1

apll_clk0

apll_clk1

apll_fp0

apll_fp1

fb_clk

ext_fb_fp

Trays

Trays

diff0

February 2008

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