74AHCT373D,112 NXP Semiconductors, 74AHCT373D,112 Datasheet - Page 11

• Manufacturer Part Number: 74AHCT373D,112
• Description: IC OCT D TRANSP LATCH 3ST 20SOIC
• Manufacturer: NXP Semiconductors
• Series: 74AHCTr
• Type: D-Typer

Specifications of 74AHCT373D,112

• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 4.5 V ~ 5.5 V
• Independent Circuits: 1
• Delay Time - Propagation: 4ns
• Current - Output High, Low: 8mA, 8mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Logic Family: AHCT
• Number Of Bits: 8
• Number Of Elements: 1
• Latch Mode: Transparent
• Polarity: Non-Inverting
• Technology: CMOS
• Package Type: SO
• Propagation Delay Time: 17ns
• Operating Supply Voltage (typ): 5V
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74AHCT373D; 74AHCT373D; 935262649112

NXP Semiconductors
Table 8.
74AHC_AHCT373_3
Product data sheet
Type
74AHC373
74AHCT373
Fig 9.
Fig 10. Data set-up and hold times
Measurement points are given in
V
Enable and disable times
Measurement points are given in
V
The shaded areas indicate when the input is permitted to change for predicable output performance.
OL
OL
Measurement points
and V
and V
OH
OH
are typical voltage output levels that occur with the output load.
are typical voltage output levels that occur with the output load.
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
Qn output
Qn output
Dn input
LE input
OE input
Input
V
0.5
1.5 V
M
GND
GND
V
V
GND
GND
V
V
I
I
V
Table
Table
V
OH
CC
OL
CC
V
I
8.
8.
V
M
V
enabled
outputs
Rev. 03 — 20 May 2008
M
t
t
su
PLZ
t
PHZ
Output
V
0.5
0.5
M
t
V
h
V
M
X
V
V
V
Y
CC
CC
74AHC373; 74AHCT373
disabled
outputs
Octal D-type transparant latch; 3-state
t
t
PZL
t
V
V
V
su
PZH
X
OL
OL
+ 0.3 V
+ 0.3 V
V
t
M
h
V
M
mna814
outputs
enabled
mna813
V
V
V
Y
OH
OH
© NXP B.V. 2008. All rights reserved.
0.3 V
0.3 V
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