74AHC573D,118 NXP Semiconductors, 74AHC573D,118 Datasheet - Page 4

• Manufacturer Part Number: 74AHC573D,118
• Description: IC OCTAL D TRANSP LATCH 20SOIC
• Manufacturer: NXP Semiconductors
• Series: 74AHCr
• Type: D-Typer

Specifications of 74AHC573D,118

• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2 V ~ 5.5 V
• Independent Circuits: 1
• Delay Time - Propagation: 3.9ns
• Current - Output High, Low: 8mA, 8mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Logic Family: AHC
• Number Of Bits: 8
• Number Of Elements: 1
• Latch Mode: Transparent
• Polarity: Non-Inverting
• Technology: CMOS
• Package Type: SO
• Propagation Delay Time: 19.5ns
• Operating Supply Voltage (typ): 5V
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74AHC573D-T; 74AHC573D-T; 935263075118

NXP Semiconductors
5. Pinning information
Table 2.
74AHC_AHCT573
Product data sheet
Symbol
OE
D0 to D7
GND
LE
Q0 to Q7
V
Fig 5.
CC
Pin configuration SO20 and TSSOP20
Pin description
GND
OE
D0
D1
D2
D3
D4
D5
D6
D7
5.1 Pinning
5.2 Pin description
10
1
2
3
4
5
6
7
8
9
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
19, 18, 17, 16, 15, 14, 13, 12
20
573
001aad099
20
19
18
17
16
15
14
13
12
11
All information provided in this document is subject to legal disclaimers.
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
CC
Rev. 6 — 25 November 2010
Fig 6.
74AHC573; 74AHCT573
(1) This is not a supply pin. The substrate is attached to this
Description
output enable input (active LOW)
data input
ground (0 V)
latch enable (active HIGH)
data output
supply voltage
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Pin configuration DHVQFN20
index area
terminal 1
Octal D-type transparant latch; 3-state
D0
D1
D2
D3
D4
D5
D6
D7
Transparent top view
2
3
4
5
6
7
8
9
74AHCT573
74AHC573
GND
(1)
19
18
17
16
15
14
13
12
© NXP B.V. 2010. All rights reserved.
001aal532
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
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