CY7C335-66WC Cypress Semiconductor Corporation., CY7C335-66WC Datasheet

CY7C335-66WC

Manufacturer Part Number

CY7C335-66WC

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C335-66WC.pdf (17 pages)

2.CY7C335-66WC.pdf (17 pages)

Specifications of CY7C335-66WC

Date_code

00+

Available stocks

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Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY7C335-66WC

Manufacturer:

Quantity:

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C335-66WC

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Quantity:

780

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Meier Automation Equipment Co., Limited

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CY7C335-66WC

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CYPRESS/赛普拉斯

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Features

Cypress Semiconductor Corporation

• 100-MHz output registered operation

• Twelve I/O macrocells, each having:

• Bypass on input and output registers

• All twelve macrocell state registers can be hidden

• User configurable I/O macrocells to implement JK or

• Input multiplexer per pair of I/O macrocells allows I/O

• Four dedicated hidden registers

• Twelve dedicated registered inputs with individually

• Three separate clocks—two input clocks, two output

• Common (pin 14-controlled) or product term-controlled

• 256 product terms—32 per pair of macrocells, variable

• Global, synchronous, product term-controlled, state

Logic Block Diagram

RS flip-flops and T or D registers

pin associated with a hidden macrocell state register

to be saved for use as an input

programmable bypass option

clocks

output enable for each I/O pin

distribution

clocked by input clock

— Registered, three-state I/O pins

— Input and output register clock select multiplexer

— Feed back multiplexer

— Output enable (OE) multiplexer

OE/I

I/O

•

3901 North First Street

PROGRAMMABLE AND ARRAY

I/O

(258x68)

Functional Description

The CY7C335 is a high-performance, erasable, programma-

ble logic device (EPLD) whose architecture has been opti-

mized to enable the user to easily and efficiently construct very

high performance state machines.

The architecture of the CY7C335, consisting of the user-con-

figurable output macrocell, bidirectional I/O capability, input

registers, and three separate clocks, enables the user to de-

sign high-performance state machines that can communicate

either with each other or with microprocessors over bidirec-

tional parallel buses of user-definable widths.

The four clocks permit independent, synchronous state ma-

chines to be synchronized to each other.

The user-configurable macrocells enable the designer to des-

ignate JK-, RS-, T-, or D-type devices so that the number of

product terms required to implement the logic is minimized.

The CY7C335 is available in a wide variety of packages in-

cluding 28-pin, 300-mil plastic and ceramic DIPs, PLCCs, and

LCCs.

• 28-pin, 300-mil DIP, LCC, PLCC

• Erasable and reprogrammable

• Programmable security bit

Universal Synchronous EPLD

— 2-ns input set-up and 9-ns output register clock to

— 10-ns input register clock to state register clock

output

I/O

•

San Jose

I/O

July 1991 – Revised March 26, 1997

•

CA 95134

/CLK3

I/O

/CLK2

I/O

•

CY7C335

CLK1

fax id: 6018

I/O

408-943-2600

C335–1

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