74AHC123APW,118 NXP Semiconductors, 74AHC123APW,118 Datasheet

IC DUAL RETRIG MULTIVIB 16TSSOP

74AHC123APW,118

Manufacturer Part Number
74AHC123APW,118
Description
IC DUAL RETRIG MULTIVIB 16TSSOP
Manufacturer
NXP Semiconductors
Series
74AHCr
Datasheet

Specifications of 74AHC123APW,118

Logic Type
Monostable
Package / Case
16-TSSOP
Independent Circuits
2
Schmitt Trigger Input
No
Propagation Delay
5.1ns
Current - Output High, Low
8mA, 8mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Elements Per Chip
2
Logic Family
AHC
Propagation Delay Time
24.1 ns, 14 ns
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
5 V
Number Of Elements
2
Operating Temperature Classification
Automotive
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (typ)
5V
Operating Temperature (min)
-40C
Operating Temperature (max)
125C
Technology
CMOS
Abs. Propagation Delay Time
32ns
Operating Supply Voltage (min)
4.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74AHC123APW-T
74AHC123APW-T
935265564118

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74AHC123APW,118
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1. General description
2. Features
The 74AHC123A; 74AHCT123A are high-speed Si-gate CMOS devices and are pin
compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC123A; 74AHCT123A are dual retriggerable monostable multivibrators with
output pulse width control by three methods. The basic pulse time is programmed by
selection of an external resistor (R
capacitor are normally connected as shown in
Once triggered, the basic output pulse width may be extended by retriggering the gated
active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating
this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as
desired. Alternatively an output delay can be terminated at any time by a LOW-going edge
on input nRD, which also inhibits the triggering.
An internal connection from nRD to the input gate makes it possible to trigger the circuit by
a positive-going signal at input nRD as shown in
pulse control by retriggering and early reset. The basic output pulse width is essentially
determined by the value of the external timing components R
C
t
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall times. The 74AHC123A; 74AHCT123A is identical to the 74AHC423; 74AHCT423 but
can be triggered via the reset input.
W
EXT
= pulse width in ns; R
74AHC123A; 74AHCT123A
Dual retriggerable monostable multivibrator with reset
Rev. 02 — 18 January 2008
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than V
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulse
For 74AHC123A only: operates with CMOS input levels
For 74AHCT123A only: operates with TTL input levels
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
10 nF, the typical output pulse width is defined as: t
EXT
= external resistor in k ; C
EXT
) and capacitor (C
CC
Figure
Table
11.
3.
EXT
EXT
Figure 8
W
). The external resistor and
= external capacitor in pF.
= R
EXT
EXT
and C
and
Product data sheet
C
Figure 9
EXT
EXT
. When
where
illustrate

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74AHC123APW,118 Summary of contents

Page 1

Dual retriggerable monostable multivibrator with reset Rev. 02 — 18 January 2008 1. General description The 74AHC123A; 74AHCT123A are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AHC123AD +125 C 74AHCT123AD 74AHC123APW +125 C 74AHCT123APW 74AHC123ABQ +125 C 74AHCT123ABQ 4. Functional diagram 1RD 3 2RD 11 Fig 1. Logic symbol 74AHC_AHCT123A_2 Product data sheet 74AHC123A; 74AHCT123A Dual retriggerable monostable multivibrator with reset Name ...

Page 3

... NXP Semiconductors Fig 3. Functional diagram 74AHC_AHCT123A_2 Product data sheet 74AHC123A; 74AHCT123A Dual retriggerable monostable multivibrator with reset 1RD 2RD Rev. 02 — 18 January 2008 14 1CEXT 15 1REXT/CEXT 2CEXT 7 2REXT/CEXT 001aaa610 © NXP B.V. 2008. All rights reserved ...

Page 4

... NXP Semiconductors For minimum noise generation it is recommended to ground pins 6 (2CEXT) and 14 (1CEXT) externally to pin 8 (GND). Fig 4. Functional diagram 74AHC_AHCT123A_2 Product data sheet 74AHC123A; 74AHCT123A Dual retriggerable monostable multivibrator with reset Rev. 02 — 18 January 2008 nREXT/CEXT V CC © NXP B.V. 2008. All rights reserved. ...

Page 5

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74AHC123A 74AHCT123A 1RD 2CEXT 6 2REXT/CEXT 7 GND 8 Fig 5. Pin configuration SO16, TSSOP16 5.2 Pin description Table 2. Pin description Symbol Pin 1RD 2CEXT 6 2REXT/CEXT 7 GND 2RD 1CEXT 14 1REXT/CEXT 74AHC_AHCT123A_2 Product data sheet 74AHC123A; 74AHCT123A Dual retriggerable monostable multivibrator with reset ...

Page 6

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Input nRD [ HIGH voltage level LOW voltage level don’t care; = LOW-to-HIGH transition; = HIGH-to-LOW transition; = one HIGH level output pulse; = one LOW level output pulse. [2] If the monostable multivibrator was triggered before this condition was established, the pulse will continue as programmed. ...

Page 7

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V) ...

Page 8

... NXP Semiconductors Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I supply current active state (per circuit input I capacitance C output O capacitance 74AHCT123A V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage LOW-level output ...

Page 9

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions 74AHC123A t propagation nA and and nQ; pd delay see Figure nRD to nQ and nQ; see Figure nRD to nQ and nQ (reset); see Figure 3 3.6 V ...

Page 10

... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions t pulse width inputs LOW; W see Figure inputs HIGH; see Figure inputs; nRD = LOW; see Figure outputs LOW and nQ = HIGH; C see ...

Page 11

... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions 74AHCT123A t propagation nA and and nQ; pd delay see Figure 4 5 nRD to nQ and nQ; see Figure 4 5 nRD to nQ and nQ (reset); see Figure 4 5 pulse width inputs LOW; ...

Page 12

... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions t retrigger nA to nB; C rtrig time EXT see Figure EXT see Figure 4 5 power pF dissipation V = GND capacitance External components R external V = 2.0 V EXT CC resistance V > 3 external V = 2.0 V ...

Page 13

... NXP Semiconductors 11. Waveforms V nB input M (nA LOW input (nB HIGH) nRD input t PLH nQ output output PHL Measurement points are given in Fig 7. Propagation delay input (nA, nB, nRD) to output (nQ, nQ) Table 8. Measurement points Type 74AHC123A 74AHCT123A nRD = HIGH Fig 8. Output pulse control using retrigger pulse ...

Page 14

... NXP Semiconductors nA = LOW Fig 9. Output pulse control using reset input nRD nA input nB input nRD input nREXT/CEXT nQ output nQ output Fig 10. Input and output timing 74AHC_AHCT123A_2 Product data sheet 74AHC123A; 74AHCT123A Dual retriggerable monostable multivibrator with reset nB input nRD input nQ output Rev. 02 — 18 January 2008 ...

Page 15

... NXP Semiconductors Fig 11. Timing component connections PULSE GENERATOR Test data is given in Table 9. Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistor Test selection switch Fig 12. Load circuitry for switching times Table 9. ...

Page 16

... NXP Semiconductors 12. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 17

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 18

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 19

... Dual retriggerable monostable multivibrator with reset Data sheet status Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN16 package added. ...

Page 20

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 21

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 14 Revision history ...

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