SY100S360FC Micrel Inc, SY100S360FC Datasheet

IC PARITYGEN/CHKR 8BIT 24CERPACK

SY100S360FC

Manufacturer Part Number
SY100S360FC
Description
IC PARITYGEN/CHKR 8BIT 24CERPACK
Manufacturer
Micrel Inc
Series
100Sr
Datasheets

Specifications of SY100S360FC

Logic Type
Parity Generator/Checker
Number Of Circuits
8-Bit
Voltage - Supply
4.2 V ~ 5.5 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-Cerpack
Logical Function
Parity Gen/Checker
Logic Family
ECL
Number Of Elements
1
Pin Count
24
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Technology
ECL
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Output High, Low
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
FEATURES
BLOCK DIAGRAM
Max. propagation delay of 2200ps
I
Industry standard 100K ECL levels
Extended supply voltage option:
V
Voltage and temperature compensation for improved
noise immunity
Internal 75K input pull-down resistors
15% faster than Fairchild 300K
Approximately 30% lower power than Fairchild 300K
Function and pinout compatible with Fairchild F100K
Available in 24-pin CERPACK and 28-pin PLCC
packages
EE
EE
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
min. of –70mA
0a
1a
2a
3a
4a
5a
6a
7a
0b
1b
2b
3b
4b
5b
6b
7b
I
I
= –4.2V to –5.5V
a
b
DUAL PARITY
CHECKER/
GENERATOR
Z
C
Z
a
b
1
is designed for use in high-performance ECL systems. The
inputs are segmented into two groups of nine inputs each
and the parity output is at a logic LOW when an even
number of inputs are at a logic HIGH. In each group, one of
the nine inputs (Ia, Ib) has a shorter propagation delay and,
therefore, is ideal as the expansion input for parity
generation of wider data.
comparison of two 8-bit words. A logic LOW on the C output
indicates a match. The inputs on this device have 75K
pull-down resistors.
V
DESCRIPTION
PIN CONFIGURATIONS
V
The SY100S360 is a dual parity checker/generator and
A Compare output (C) is also provided which allows
EES
I
I
I
I
I
EE
6a
7a
0b
1b
2b
12
13
14
15
16
17
18
11
19
10
20
Top View
21
9
PLCC
J28-1
22
8
23
7
24
6
I
I
I
I
I
3b
4b
7b
5b
6b
I
25
b
5
28
27
26
4
3
2
1
1
2
3
4
5
6
24
7
I
Z
V
V
V
C
Z
a
a
b
CCA
CC
CC
23
8
Top View
Flatpack
22
F24-1
9
21
10
Rev.: G
Issue Date: July, 1999
SY100S360
20
11
19
12
18
17
16
15
14
13
Amendment: /0
FINAL
I
I
I
I
I
I
5a
4a
3a
2a
1a
0a

Related parts for SY100S360FC

SY100S360FC Summary of contents

Page 1

FEATURES Max. propagation delay of 2200ps I min. of –70mA EE Industry standard 100K ECL levels Extended supply voltage option –4.2V to –5.5V EE Voltage and temperature compensation for improved noise immunity Internal 75K input pull-down resistors 15% ...

Page 2

Micrel PIN NAMES Pin Function Data Inputs (n = 1... – Z Parity Odd Outputs Compare Output V V Substrate EES for ...

Page 3

... NOTE –4.2V to –5.5V unless otherwise specified 80% 50% 20% t PHL t PLH t TLH Propagation Delay and Transition Times = V = GND CC CCA PRODUCT ORDERING CODE Ordering Code SY100S360FC SY100S360JC SY100S360JCTR 3 SY100S360 0.7 ± 0.1 ns –0.95V –1.69V t PLH 50% t PHL 80% 50% 20% t THL Package Operating Type ...

Page 4

Micrel 24 LEAD CERPACK (F24-1) 4 SY100S360 Rev. 03 ...

Page 5

... TEL This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc (408) 914-7878 http://www ...

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