MC74HC589ANG ON Semiconductor, MC74HC589ANG Datasheet - Page 7

• Manufacturer Part Number: MC74HC589ANG
• Description: IC SHIFT REGISTER 8BIT 16-DIP
• Manufacturer: ON Semiconductor
• Series: 74HCr

Specifications of MC74HC589ANG

• Logic Type: Shift Register
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Function: Universal
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Counting Sequence: Serial/Parallel to Serial
• Number Of Circuits: 2
• Logic Family: 74HC
• Propagation Delay Time: 175 ns, 100 ns, 40 ns, 30 ns
• Supply Voltage (max): 6 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Mounting Style: Through Hole
• Operating Supply Voltage: 2 V to 6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC74HC589ANGOS

OUTPUT
FUNCTION TABLE
ENABLE
Force Output into High
Impedance State
Load Parallel Data into Data
Latch
Transfer Latch Contents to
Shift Register
Contents of Input Latch and
Shift Register are Unchanged
Load Parallel Data into Data
Latch and Shift Register
Shift Serial Data into Shift
Register
Load Parallel Data in Data
Latch and Shift Serial Data
into Shift Register
LR = latch register contents
SR = shift register contents
a-h = data at parallel data inputs A-H
D
CLOCK
LATCH
= data (L, H) at serial data input S
Q
Q
H
H
Figure 3. (Serial Shift/Parallel Load = L)
Q
Operation
H
50%
10%
50%
90%
50%
50%
10%
t
t
r
w
t
t
50%
PZL
PZH
t
90%
PLH
t
Figure 5.
TLH
t
Output
Enable
t
PHZ
PLZ
H
L
L
L
L
L
L
t
PHL
t
f
t
THL
Parallel Load
Serial Shift/
A
10%
90%
X
H
H
H
H
L
L
Switching Waveforms
V
GND
V
GND
HIGH
IMPEDANCE
V
V
HIGH
IMPEDANCE
L, H,
L, H,
CC
CC
OL
OH
Latch
Clock
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MC74HC589A
Inputs
X
X
L, H ,
L, H,
Clock
Shift
7
X
X
X
PARALLEL LOAD
SERIAL SHIFT/
Serial
CLOCK
U = remains unchanged
X = don't care
Z = high impedance
*
Input
SHIFT
S
X
X
X
X
X
D
D
A
= depends on Latch Clock input
Figure 4. (Serial Shift/Parallel Load = H)
Q
H
Parallel
Q
Inputs
A-H
a-h
a-h
a-h
H
50%
X
X
X
X
50%
t
PLH
50%
t
Contents
w
t
t
w
Latch
PLH
Data
Figure 6.
a-h
a-h
a-h
50%
X
U
U
*
1/f
max
Resulting Function
t
SR
SR
PHL
LR
Contents
Register
SR
SR
N
N
N
Shift
→ SR
→ SR
a-h
A
A
→ SR
U
U
X
= D,
= D,
t
PHL
50%
N+1
N+1
N
SR
SR
Output
V
GND
G
G
LR
CC
Q
→ SR
→ SR
U
U
Z
h
H
H
V
GND
CC
H
H