AD9467-FMC-250EBZ Analog Devices, AD9467-FMC-250EBZ Datasheet

AD9467-FMC-250EBZ

Manufacturer Part Number

AD9467-FMC-250EBZ

Description

EVAL BOARD/AD9467 16 BIT 250 MSPS FMC EVAL BD

Manufacturer

Analog Devices

Datasheet

1.AD9467-FMC-250EBZ.pdf (32 pages)

Specifications of AD9467-FMC-250EBZ

Pack_quantity

Comm_code

85437090

Lead_time

Eccn

3A001A5A5

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Data Sheet

FEATURES

75.5 dBFS SNR to 210 MHz at 250 MSPS

90 dBFS SFDR to 300 MHz at 250 MSPS

SFDR at 170 MHz at 250 MSPS

60 fs rms jitter

Excellent linearity at 250 MSPS

2 V p-p to 2.5 V p-p (default) differential

Integrated input buffer

External reference support option

Clock duty cycle stabilizer

Output clock available

Serial port control

LVDS outputs (ANSI-644 compatible)

1.8 V and 3.3 V supply operation

APPLICATIONS

Multicarrier, multimode cellular receivers

Antenna array positioning

Power amplifier linearization

Broadband wireless

Radar

Infrared imaging

Communications instrumentation

GENERAL DESCRIPTION

The AD9467 is a 16-bit, monolithic, IF sampling analog-to-

digital converter (ADC). It is optimized for high performance

over wide bandwidths and ease of use. The product operates at

a 250 MSPS conversion rate and is designed for wireless

receivers, instrumentation, and test equipment that require a

high dynamic range.

The ADC requires 1.8 V and 3.3 V power supplies and a low

voltage differential input clock for full performance operation.

No external reference or driver components are required for

many applications. Data outputs are LVDS compatible (ANSI-644

compatible) and include the means to reduce the overall current

needed for short trace distances.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

92 dBFS at −1 dBFS

100 dBFS at −2 dBFS

full-scale input (programmable)

Selectable output data format

DNL = ±0.5 LSB typical

INL = ±3.5 LSB typical

Built-in selectable digital test pattern generation

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

CLK+

A data clock output (DCO) for capturing data on the output is

provided for signaling a new output bit.

The internal power-down feature supported via the SPI typically

consumes less than 5 mW when disabled.

Optional features allow users to implement various selectable

operating conditions, including input range, data format select,

and output data test patterns.

The AD9467 is available in a Pb-free, 72-lead, LFCSP specified

over the −40°C to +85°C industrial temperature range.

PRODUCT HIGHLIGHTS

CLK–

VIN+

VIN–

16-Bit, 200 MSPS/250 MSPS

Analog-to-Digital Converter

IF optimization capability used to improve SFDR.

Outstanding SFDR performance for IF sampling

applications such as multicarrier, multimode 3G, and 4G

cellular base station receivers.

Ease of use: on-chip reference, high input impedance

buffer, adjustable analog input range, and an output clock

to simplify data capture.

Packaged in a Pb-free, 72-lead LFCSP package.

Clock duty cycle stabilizer (DCS) maintains overall ADC

performance over a wide range of input clock pulse widths.

Standard serial port interface (SPI) supports various

product features and functions, such as data formatting

(offset binary, twos complement, or Gray coding).

AGND

AD9467

MANAGEMENT

AND TIMING

BUFFER

FUNCTIONAL BLOCK DIAGRAM

CLOCK

AVDD1

AVDD2

AVDD3 SPIVDD

PIPELINE

Figure 1.

ADC

XVREF

REF

STAGING

OUTPUT

DRVDD DRGND

LVDS

AD9467

www.analog.com

CSB

SDIO

SCLK

OR+/OR–

D15+/D15–

D0+/D0–

DCO+/DCO–

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