AK4103A_09 AKM [Asahi Kasei Microsystems], AK4103A_09 Datasheet
AK4103A_09
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AK4103A_09 Summary of contents
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The AK4103A is a digital audio transmitter (DIT) which supports data rate up to 192kHz sample rate operation. The AK4103A supports AES3, IEC60958, S/PDIF & EIAJ CP1201 interface standards. The AK4103A accepts audio data, auxiliary information data and etc, which ...
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Block Diagram BICK LRCK SDTI FS0 FS1 FS2 FS3 MS0251-E-01 Prescaler Audio Serial Interface Biphase Encoder CRCC Generator Host Serial Interface - 2 - [AK4103A] TXP TXN 2009/01 ...
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Ordering Guide -40 ∼ +85°C AK4103AVF AKD4103A Evaluation Board for AK4103A ■ Pin Layout V1 1 TRANS 2 PDN 3 MCLK 4 SDTI 5 BICK 6 LRCK 7 FS0/CSN 8 FS1/CDTI 9 FS2/CCLK 10 FS3/CDTO ■ ...
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No. Pin Name I TRANS I 3 PDN I 4 MCLK I 5 SDTI I 6 BICK I/O 7 LRCK I/O 8 FS0 I CSN I AKMODE I 9 FS1 I CDTI I 10 FS2 I ...
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Note 3) Parameter Power Supply Input Current (All pins except supply pins) Input Voltage Ambient Operating Temperature Storage Temperature Note 3. All voltages with respect to ground. WARNING: Operation at or beyond these limits may results in permanent damage ...
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VDD=4.75~5.25V; C =20pF) L Parameter Master Clock Timing Frequency Duty Cycle LRCK Timing Frequency Duty Cycle at Slave Mode Duty Cycle at Master Mode Audio Interface Timing Slave Mode BICK Period BICK Pulse Width Low Pulse Width High LRCK ...
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Timing Diagram MCLK LRCK BICK LRCK BICK SDTI LRCK BICK SDTI MS0251-E-01 1/fCLK tCLKH tCLKL 1/fs tBCK tBCKH tBCKL Clock Timing tBLR tLRB tSDS tSDH Audio Interface Timing (Slave Mode) tMBLR tSDS tSDH Audio Interface Timing (Master Mode) - ...
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CSN CCLK CDTI CDTO CSN CCLK CDTI D3 CDTO CSN CCLK A1 CDTI Hi-Z CDTO (with pull-down resistor) MS0251-E-01 tCSS tCCKL tCCKH tCDH tCDS C1 C0 Hi-Z (with pull-down resistor) WRITE/READ Command Input Timing tCSH WRITE Data ...
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CSN CCLK CDTI CDTO D3 PDN MS0251-E- READ Data Output Timing 2 tPDW Power-down & Reset Timing - 9 - [AK4103A] tCSW VIH VIL tCSH VIH VIL VIH VIL tCCZ 50%VDD VIL 2009/01 ...
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General Description The AK4103A is a monolithic CMOS circuit that biphase-encodes and transmits audio data, auxiliary information data and etc according to the AES3, IEC60958, S/PDIF and EIAJ CP1201 interface standards. There is one set of stereo channels that ...
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Synchronous Mode (hardware controlled) The AK4103A when configured in synchronous mode accepts bit audio samples through the audio serial port and provides dedicated pins for the control data and allows all channel status, user data and ...
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BLS C (or U,V) C(R191) LRCK SDTI 2 (except I S) SDTI Figure 2. Audio routing mode timing (AKMODE pin = “1”) ■ Block Start Timing Normal mode In normal mode (TRANS pin = “L”), the block ...
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Serial Ports Normal mode In normal mode (TRANS pin = “L”), the C, U and V bits are captured (either from the pins, in synchronous mode, or the control registers, in the asynchronous mode) in the ...
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Channel 1 LRCK BICK C,U,V ■ Audio Serial Interface The audio serial interface is used to input audio data and consists of three pins: Bit Clock (BICK), Word Clock (LRCK) & Data pin (SDTI). LRCK indicates the particular channel, left ...
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LRCK( BICK(i) SDTI(i) 17:MSB, 0:LSB LRCK( BICK(i) SDTI(i) 19:MSB, 0:LSB LRCK( BICK(i) 23 SDTI(i) 23:MSB, 0:LSB MS0251-E- Lch Data Figure ...
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LRCK BICK SDTI(i) 23:MSB, 0:LSB LRCK BICK SDTI(i) 23:MSB, 0:LSB MS0251-E- Lch Data ...
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Sampling frequency setting Bits 3-0 of Channel Status Byte 3 in consumer mode can be set by FS3-0 pins. Also bits 7-6 of Channel Status Byte 0 and bits 6-3 of Channel Status Byte 4 in professional mode can ...
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Data Transmission Format Data transmitted on the TX outputs is formatted in blocks as shown in frame of data contains two sub-frames. A sub-frame consists of 32 bits of information. Each data bit received is coded using a bi-phase ...
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Line Driver There is an RS422 line driver on chip. The AES3 specification states that the line driver shall have a balanced output with an internal impedance of 110 ohms ±20% and also requires a balanced output drive capability ...
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Serial Control Interface In asynchronous mode, four of the dual function pins become CSN, CCLK, CDTI and CDTO wire microprocessor interface. The internal 18 byte control register can then be read and written. The contents of the ...
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Register Map Addr Register Name 00H Clock/Format Control 01H Validity/fs Control A-channel C-bit buffer 02H for Byte 0 A-channel C-bit buffer 03H for Byte 1 A-channel C-bit buffer 04H for Byte 2 A-channel C-bit buffer 05H for Byte 3 ...
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Register Definitions Addr Register Name 00H Clock/Format Control R/W Default RSTN: Timing Reset. 0: Resets the internal frame and bit counters. Control registers are not initialized. TXP pin is “H” and TXN pin is “L”. In normal mode, BLS ...
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Addr Register Name A-channel C-bit buffer 02H for Byte 0 B-channel C-bit buffer 06H for Byte 0 R/W Default C0-7: Channel Status Byte 0 Default: “00100000” Addr Register Name A-channel C-bit buffer 03H for Byte 1 B-channel C-bit buffer 07H ...
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Addr Register Name 0AH- A-channel U-bit buffer 0DH for Byte 0-3 0EH- B-channel U-bit buffer 11H for Byte 0-3 R/W Default U0-31: User Data Default: all “0” ■ Default values of control registers Bits CRCE DIF2-0 CKS1-0 V1 FS3-0 MUTEN ...
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VSOP (Unit: mm) *7.8±0. +0.10 0.22 –0.05 Seating Plane NOTE: Dimension "*" does not include mold flash. ■ Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0251-E-01 PACKAGE 13 12 ...
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Date (YY/MM/DD) Revision 03/07/28 00 09/01/09 01 MS0251-E-01 MARKING AKM AK4103AVF AAXXXX Contents of AAXXXX AA: Lot# XXXX: Date Code REVISION HISTORY Reason Page Contents First Edition Specification 25 PACKAGE Change The pin width dimension was changed ...
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These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status ...